Fairchild Semiconductor Electronic Components Datasheet


FDZ1323NZ

MOSFET



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September 2014
FDZ1323NZ
Common Drain N-Channel 2.5 V PowerTrench® WL-CSP MOSFET
20 V, 10 A, 13 mΩ
Features
„ Max rS1S2(on) = 13 mΩ at VGS = 4.5 V, IS1S2 = 1 A
„ Max rS1S2(on) = 13 mΩ at VGS = 3.8 V, IS1S2 = 1 A
„ Max rS1S2(on) = 16 mΩ at VGS = 3.1 V, IS1S2 = 1 A
„ Max rS1S2(on) = 18 mΩ at VGS = 2.5 V, IS1S2 = 1 A
„ Occupies only 3 mm2 of PCB area
„ Ultra-thin package: less than 0.35 mm height when mounted
to PCB
„ High power and current handling capability
„ HBM ESD protection level > 3.6 kV (Note 3)
„ RoHS Compliant
General Description
This device is designed specifically as a single package solution
for Li-Ion battery pack protection circuit and other ultra-portable
applications. It features two common drain N-channel
MOSFETs, which enables bidirectional current flow, on
Fairchild’s advanced PowerTrench® process with state of the art
“low pitch” WLCSP packaging process, the FDZ1323NZ
minimizes both PCB space and rS1S2(on). This advanced
WLCSP MOSFET embodies a breakthrough in packaging
technology which enables the device to combine excellent
thermal transfer characteristics, ultra-low profile packaging, low
gate charge and low rS1S2(on).
Applications
„ Battery management
„ Load switch
„ Battery protection
PIN1
PIN1
S1
S1
G1
S2
G2
S2
S1
G1
TOP
WL-CSP 1.3X2.3
BOTTOM
G2
S2
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VS1S2
VGS
IS1S2
PD
TJ, TSTG
Parameter
Source1 to Source2 Voltage
Gate to Source Voltage
Source1 to Source2 Current -Continuous TA = 25°C
-Pulsed
Power Dissipation
TA = 25°C
Power Dissipation
TA = 25°C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 1a)
(Note 1b)
Ratings
20
±12
10
40
2
0.5
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
(Note 1b)
62
257
°C/W
Device Marking
EC
Device
FDZ1323NZ
Package
WL-CSP 1.3X2.3
Reel Size
7 ’’
Tape Width
8 mm
Quantity
5000 units
©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
1
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
IS1S2
IGSS
Zero Gate Voltage Source1 to Source2
Current
Gate to Source Leakage Current
VS1S2 = 16 V, VGS = 0 V
VGS = ±12 V, VS1S2 = 0 V
1 μA
±10 μA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VS1S2, IS1S2 = 250 μA
0.4 0.9 1.2
V
VGS = 4.5 V, IS1S2 = 1 A
4.5 9.7 13
VGS = 3.8 V, IS1S2 = 1 A
5.5 10 13
rS1S2(on)
Static Source1 to Source2 On Resistance VGS = 3.1 V, IS1S2 = 1 A
7 11 16 mΩ
VGS = 2.5 V, IS1S2 = 1 A
VGS = 4.5 V, IS1S2 = 1 A,TJ = 125 oC
8
13 18
13 20
gFS Forward Transconductance
VS1S2 = 5 V, IS1S2 = 1 A
9S
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VS1S2 = 10 V, VGS = 0 V,
f = 1 MHz
1545
269
252
2055
405
380
pF
pF
pF
Switching Characteristics
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source1 Gate Charge
Gate to Source2 “Miller” Charge
VS1S2 = 10 V, IS1S2 = 1 A,
VGS = 4.5 V, RGEN = 6 Ω
VS1S2 = 10 V, IS1S2 = 1 A,
VG1S1 = 4.5 V, VG2S2 = 0 V
12 22 ns
13 23 ns
34 54 ns
13 23 ns
17 24 nC
1.9 nC
5.4 nC
Source1 to Source2 Diode Characteristics
Ifss Maximum Continuous Source1 to Source2 Diode Forward Current
Vfss
Source1 to Source2 Diode Forward
Voltage
VG1S1 = 0 V, VG2S2 = 4.5 V,
Ifss = 1 A
(Note 2)
1
0.6 1.2
A
V
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a. 62 °C/W when mounted on
a 1 in2 pad of 2 oz copper.
b. 257 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 us, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only protection against ESD. No gate overvoltage rating is implied.
©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
2
www.fairchildsemi.com


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Typical Characteristics TJ = 25°C unless otherwise noted
40
VG1S1 = 4.5 V
VG1S1 = 3.8 V
30
VG1S1 = 3.1 V
40
VGS = 4.5 V
VGS = 3.8 V
30
VGS = 3.1 V
VGS = 2.5 V
20
10
0
0.0
VG1S1 = 2.5 V
VG1S1 = 2 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VG2S2 = 4.5 V
0.2 0.4
0.6
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
Figure 1. On-Region Characteristics
20
VGS = 2 V
10
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0 0.2 0.4 0.6 0.8 1.0
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
Figure 2. On-Region Characteristics
2.0
1.5
VG1S1 = 2 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VG2S2 = 4.5 V
VG1S1 = 2.5 V
1.0
VG1S1 = 3.1 V VG1S1 = 3.8 V VG1S1 = 4.5 V
0.5
0
10 20 30 40
IS1S2, SOURCE1 TO SOURCE2 CURRENT (A)
Figure 3. Normalized On-Resistance vs Source1
to Source2 Current and Gate Voltage
2.0
VGS = 2 V
1.5
VGS = 2.5 V
VGS = 3.1 V
1.0
PULSE DURATION = 80 μs VGS = 3.8 V VGS = 4.5 V
DUTY CYCLE = 0.5% MAX
0.5
0
10 20 30 40
IS1S2, SOURCE1 TO SOURCE2 CURRENT (A)
Figure 4. Normalized On-Resistance vs Source1
to Source2 Current and Gate Voltage
1.6
IS1S2 = 1 A
VGS = 4.5 V
1.4
1.2
1.0
0.8
0.6
-75
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 5. Normalized On Resistance
vs Junction Temperature
60
PULSE DURATION = 80 μs
50 DUTY CYCLE = 0.5% MAX
IS1S2 = 1 A
40
30
TJ = 125 oC
20
10
0
1.0
TJ = 25 oC
1.5 2.0 2.5 3.0 3.5 4.0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6. On Resistance vs Gate to
Source Voltage
4.5
©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
3
www.fairchildsemi.com


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Typical Characteristics TJ = 25°C unless otherwise noted
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
VS1S2 = 5 V
20
TJ = 150 oC
TJ = 25 oC
10
TJ = -55 oC
100
VG1S1 = 0 V, VG2S2 = 4.5 V
10 TJ = 150 oC
1
TJ = 25 oC
TJ = -55 oC
0
0.5 1.0 1.5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
2.0
4.5
VG2S2 = 0 V
IS1S2 = 1 A
VS1S2 = 8 V
3.0
VS1S2 = 10 V
1.5
VS1S2 = 12 V
0.0
0 4 8 12 16
Qg, GATE CHARGE (nC)
Figure 9. Gate Charge Characteristics
20
10-1
10-2
10-3
10-4
10-5
VS1S2 = 0 V
TJ = 125 oC
10-6
10-7
10-8
10-9
10-10
0
TJ = 25 oC
369
12
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 11. Gate Leakage Current
vs Gate to Source Voltage
15
0.1
0.0 0.2 0.4 0.6 0.8 1.0
Vfss, BODY DIODE FORWARD VOLTAGE (V)
Figure 8. Source1 to Source2 Diode
Forward Voltage vs Source Current
1.2
5000
Ciss
1000
Coss
f = 1 MHz
VGS = 0 V
100
0.1
Crss
1
10
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
Figure10. Capacitance vs Source1
to Source2 Voltage
20
50
10
1
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 257 oC/W
TA = 25 oC
0.01
0.01 0.1
CURVE BENT TO
MEASURED DATA
1 10
1 ms
10 ms
100 ms
1s
10 s
DC
100
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
Figure 12. Forward Bias Safe
Operating Area
©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
4
www.fairchildsemi.com


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Typical Characteristics TJ = 25°C unless otherwise noted
100
10
SINGLE PULSE
RθJA = 257 oC/W
1 TA = 25 oC
0.4
10-3
2
1
0.1
0.01
0.001
10-4
10-2
10-1
100
101
t, PULSE WIDTH (sec)
Figure 13. Single Pulse Maximum Power Dissipation
100
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA = 257 oC/W
(Note 1b)
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 14. Junction-to-Ambient Transient Thermal Response Curve
1000
1000
©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
5
www.fairchildsemi.com


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Dimensional Outline and Pad Layout
Pin Definations:
Gate
B1, B2
Source1
A1, C1
Product Specific Dimensions:
D
2.3 mm
E
1.3 mm
X
0.315 mm
Source2
A2, C2
Y
0.49 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_UCBEA-006
©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
6
www.fairchildsemi.com


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®*
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©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I71
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