Fairchild Semiconductor Electronic Components Datasheet


FDS8958B

MOSFET



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FDS8958B
Dual N & P-Channel PowerTrench® MOSFET
Q1-N-Channel: 30 V, 6.4 A, 26 mQ2-P-Channel: -30 V, -4.5 A, 51 m
November 2013
Features
Q1: N-Channel
„ Max rDS(on) = 26 mat VGS = 10 V, ID = 6.4 A
„ Max rDS(on) = 39 mat VGS = 4.5 V, ID = 5.2 A
Q2: P-Channel
„ Max rDS(on) = 51 mat VGS = -10 V, ID = -4.5 A
„ Max rDS(on) = 80 mat VGS = -4.5 V, ID = -3.3 A
„ HBM ESD protection level > 3.5 kV (Note 3)
General Description
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild Semiconductor's
advanced PowerTrench® process th at has been especially
tailored to minimize on-state resistan ce and yet maintain
superior switching performance.
These devices are well suite d for low voltage and battery
powered applications where low in-line power loss and fast
switching are required.
Application
„ RoHS Compliant
„ DC-DC Conversion
„ BLU and motor drive inverter
D2
D1
D1
D2
Pin 1
G2
S2
G1
S1
D2 5
D2 6
D1 7
D1 8
Q2
Q1
4 G2
3 S2
2 G1
1 S1
SO-8
MOSFET Maximum Ratings TC = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
EAS
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
Single Pulse Avalanche Energy
Operating and Storage Junction Temperature Range
TA = 25 °C
TA = 25 °C
TA = 25 °C
(Note 1a)
(Note 1b)
(Note 4)
Thermal Characteristics
Q1 Q2
30 -30
±20 ±25
6.4 -4.5
30 -30
2.0
1.6
0.9
18 5
-55 to +150
Units
V
V
A
W
mJ
°C
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1)
(Note 1a)
40
78
°C/W
Device Marking
FDS8958B
Device
FDS8958B
Package
SO-8
Reel Size
13 ”
Tape Width
12 mm
Quantity
2500 units
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
1
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
TJ
IDSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250 µA, VGS = 0 V
ID = -250 µA, VGS = 0 V
ID = 250 µA, referenced to 25 °C
ID = -250 µA, referenced to 25 °C
VDS = 24 V, VGS = 0 V
VDS = -24 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VGS = ±25 V, VDS = 0 V
Q1 30
Q2 -30
V
Q1
Q2
24
-21
mV/°C
Q1
Q2
1
-1
µA
Q1 ±100 nA
Q2 ±10 µA
On Characteristics
VGS(th)
VGS(th)
TJ
rDS(on)
gFS
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 µA
VGS = VDS, ID = -250 µA
Q1 1.0 2.0
Q2 -1.0 -1.9
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 µA, referenced to 25 °C
ID = -250 µA, referenced to 25 °C
Q1
Q2
-6
5
VGS = 10 V, ID = 6.4 A
VGS = 4.5 V, ID = 5.2 A
Static Drain to Source On Resistance
VGS = 10 V, ID = 6.4A, TJ = 125 °C
VGS = -10 V, ID = -4.5 A
VGS = -4.5 V, ID = -3.3 A
VGS = -10 V, ID = -4.5 A, TJ = 125 °C
Q1
Q2
21
29
31
38
60
53
Forward Transconductance
VDD = 5 V, ID = 6.4 A
VDD = -5 V, ID = -4.5 A
Q1 20
Q2 10
3.0
-3.0
V
mV/°C
26
39
39
51
m
80
72
S
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
Q1
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2
VDS = -15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
405 540
570 760
75 100
115 155
55 80
100 150
2.4
4.4
pF
pF
pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg(TOT)
Total Gate Charge
Qg(TOT)
Total Gate Charge
Qgs Gate to Source Charge
Qgd Gate to Drain “Miller” Charge
Q1
VDD = 15 V, ID = 6.4 A,
VGS = 10 V, RGEN = 6
Q2
VDD = -15 V, ID = -4.5 A,
VGS = -10 V, RGEN = 6
VGS = 10 V
VGS = -10 V
VGS = 4.5 V
VGS = -4.5 V
Q1
VDD = 15 V,
ID = 6.4 A
Q2
VDD = -15 V,
ID = -4.5 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
4.3 10
6.0 12
ns
2.0 10
6.0 12
ns
12
17
22
30
ns
2.0 10
7.0 14
ns
8.3
14
12
19
nC
4.1
7.0
5.8
9.6
nC
1.3
1.9
nC
1.7
3.6
nC
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
2
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Drain-Source Diode Characteristics
VSD
Source to Drain Diode
Forward Voltage
VGS = 0 V, IS = 1.3 A
VGS = 0 V, IS = -1.3 A
(Note 2)
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
Q1
IF = 6.4 A, di/dt = 100 A/µs
Q2
IF = -4.5 A, di/dt = 100 A/µs
Q1
Q2
Q1
Q2
Q1
Q2
0.8 1.2
-0.8 -1.2
17 30
20 36
6 12
8 16
V
ns
nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a) 78 °C/W when
mounted on a 1 in2
pad of 2 oz copper
b) 135 °C/W when
mounted on a
minimun pad
2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
4. UIL condition: Starting TJ = 25 °C, L = 1 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V . (Q1)
Starting TJ = 25 °C, L = 1 mH, IAS = -4 A, VDD = -27 V, VGS = -10 V. (Q2)
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
3
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
30
VGS = 10 V
24
VGS = 6 V
VGS = 4.5 V
18 VGS = 4 V
12
6
0
0
VGS = 3.5 V
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
0.5 1.0 1.5 2.0 2.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
3.0
Figure 1. On Region Characteristics
3.0
VGS = 3.5 V
2.5
2.0
VGS = 4 V
VGS = 4.5 V
1.5
1.0
0.5
0
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
6 12 18
ID, DRAIN CURRENT (A)
VGS = 6 V
VGS = 10 V
24 30
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.8
ID = 6.4 A
1.6 VGS = 10 V
1.4
1.2
1.0
0.8
0.6
0.4
-75
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs Junction Temperature
75
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
60
ID = 3.2 A
45
30
15
2
TJ = 125 oC
TJ = 25 oC
468
VGS, GATE TO SOURCE VOLTAGE (V)
10
Figure 4. On-Resistance vs Gate to
Source Voltage
30
PULSE DURATION = 80 µs
25 DUTY CYCLE = 0.5% MAX
VDS = 5 V
20
15
10
5
0
1
TJ = 125 oC
TJ = 25 oC
TJ = -55 oC
2345
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
6
30
VGS = 0 V
10
TJ = 125 oC
1
0.1
TJ = 25 oC
0.01
0.2
TJ = -55 oC
0.4 0.6 0.8 1.0 1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
4
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 6.4 A
8
VDD = 10 V
6
VDD = 15 V
4
VDD = 20 V
2
0
0 2 4 6 8 10
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
1000
Ciss
100 Coss
Crss
f = 1 MHz
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. CapacitancevsDrain
to Source Voltage
30
9
8
7
6
5
4 TJ = 25 oC
3
2
TJ = 125 oC
1
0.001
0.01 0.1
1
10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
500
100
100
THIS AREA IS
LIMITED BY rDS(on)
10
0.1 ms
1
0.1
0.01
0.01
SINGLE PULSE
TJ = MAX RATED
RθJA = 135 oC/W
TA = 25 oC
1 ms
10 ms
100 ms
1s
10 s
DC
0.1 1 10
VDS, DRAIN to SOURCE VOLTAGE (V)
100
Figure 10. Forward Bias Safe
Operating Area
100 VGS = 10 V
10
SINGLE PULSE
RθJA = 135 oC/W
TA = 25 oC
1
0.5
10-4
10-3
10-2
10-1
1
10
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
100
1000
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
5
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
1 DUTY CYCLE-DESCENDING ORDER
0.1
0.01
0.001
10-4
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA = 135 oC/W
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
1000
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
6
www.fairchildsemi.com


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Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
30
24
18
12
6
0
0.0
VGS = -10 V
VGS = -6 V
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
VGS = -4.5 V
VGS = -4 V
VGS = -3.5 V
0.5 1.0 1.5 2.0 2.5
-VDS, DRAIN TO SOURCE VOLTAGE (V)
3.0
Figure 15. On- Region Characteristics
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VGS = -3.5 V
VGS = -4 V
VGS = -4.5 V
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5%MAX
VGS = -6 V
6 12 18
-ID, DRAIN CURRENT (A)
VGS = -10 V
24 30
Figure 16. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
ID = -4.5 A
VGS = -10 V
1.4
1.2
1.0
0.8
0.6
-75
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 17. Normalized On-Resistance
vs Junction Temperature
200
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
160
ID = -2.3 A
120
80
40
0
2
TJ = 125 oC
TJ = 25 oC
468
-VGS, GATE TO SOURCE VOLTAGE (V)
10
Figure 18. On-Resistance vs Gate to
Source Voltage
30
PULSE DURATION = 80 µs
25 DUTY CYCLE = 0.5% MAX
VDS = -5 V
20
TJ = -55 oC
15
TJ = 25 oC
TJ = 125 oC
10
5
0
12345
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 19. Transfer Characteristics
6
30
VGS = 0 V
10
TJ = 125 oC
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.2 0.4 0.6 0.8 1.0 1.2 1.4
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 20. Source to Drain Diode
Forward Voltage vs Source Current
1.6
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
7
www.fairchildsemi.com


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Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
10
ID = -4.5 A
8
6
4
2
VDD = -10 V
VDD = -15 V
VDD = -20 V
0
0 3 6 9 12 15
Qg, GATE CHARGE (nC)
Figure 21. Gate Charge Characteristics
8
7
6
5
4 TJ = 25 oC
3
2
TJ = 125 oC
1
0.01
0.1 1
tAV, TIME IN AVALANCHE (ms)
10
Figure 23. Unclamped Inductive
Switching Capability
100
THIS AREA IS
10 LIMITED BY rDS(on)
0.1 ms
1
0.1
0.01
0.01
SINGLE PULSE
TJ = MAX RATED
RθJA = 135 oC/W
TA = 25 oC
1 ms
10 ms
100 ms
1s
10 s
DC
0.1 1 10
-VDS, DRAIN to SOURCE VOLTAGE (V)
100
Figure 25. Forward Bias Safe
Operating Area
2000
1000
Ciss
Coss
100
f = 1 MHz
Crss
VGS = 0 V
30
0.1
1
10
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 22. Capacitance vs Drain
to Source Voltage
30
10-2
10-3 VGS = 0V
10-4
10-5 TJ = 125oC
10-6
10-7
10-8 TJ = 25oC
10-9
0
5 10 15 20 25 30
-VGS, GATE TO SOURCE VOLTAGE(V)
35
Figure 24. Ig vs Vgs
200
100 VGS = -10 V
SINGLE PULSE
RθJA = 135 oC/W
10 TA = 25 oC
1
0.5
10-4
10-3
10-2
10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 26. Single Pulse Maximum Power
Dissipation
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
8
www.fairchildsemi.com


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Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
2
1
0.1
0.01
0.002
10-4
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA = 135 oC/W
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 27. Junction-to-Ambient Transient Thermal Response Curve
1000
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
9
www.fairchildsemi.com


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Physical Dimensions
4.90±0.10 A
(0.635)
85
B
6.00±0.20
3.90±0.10
1.75
0.65
5.60
PIN ONE
INDICATOR
1
0.175±0.75
4
1.27
0.25
1.27
C B A LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.75 MAX
C
0.42±0.09
0.22±0.30
0.10
OPTION A - BEVEL EDGE
R0.10
R0.10
0.65±0.25
(0.86) x 45°
GAGE PLANE
0.36
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08Arev15
F) FAIRCHILD SEMICONDUCTOR.
Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150-inch Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/M0/M08A.pdf.
© 2008 Fairchild Semiconductor Corporation
FDS8958B Rev. C
10
www.fairchildsemi.com


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© 2008 Fairchild Semiconductor Corporation
FDS8958B Rev. C
11
www.fairchildsemi.com


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