Fairchild Semiconductor Electronic Components Datasheet


FDT86102LZ

MOSFET



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November 2010
FDT86102LZ
N-Channel PowerTrench® MOSFET
100 V, 6.6 A, 28 mΩ
Features
„ Max rDS(on) = 28 mΩ at VGS = 10 V, ID = 6.6 A
„ Max rDS(on) = 38 mΩ at VGS = 4.5 V, ID = 5.5 A
„ HBM ESD protection level > 6 kV typical (Note 4)
„ Very low Qg and Qgd compared to competing trench
technologies
„ Fast switching speed
„ 100% UIL Tested
„ RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that has
been especially tailored to minimize the on-state resistance and
switching loss. G-S zener has been added to enhance ESD
voltage level.
Applications
„ DC-DC conversion
„ Inverter
„ Synchronous Rectifier
D
SOT-223
S
D
G
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation
TA = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 3)
(Note 1a)
(Note 1b)
Ratings
100
±20
6.6
40
84
2.2
1.0
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1)
(Note 1a)
12
55
°C/W
Device Marking
86102LZ
Device
FDT86102LZ
Package
SOT-223
Reel Size
13 ’’
Tape Width
12 mm
Quantity
2500 units
©2010 Fairchild Semiconductor Corporation
FDT86102LZ Rev. C
1
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
100 V
70 mV/°C
1 μA
±10 μA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
1.0 1.4 3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
-6 mV/°C
VGS = 10 V, ID = 6.6 A
22 28
rDS(on)
Static Drain to Source On Resistance
VGS = 4.5 V, ID = 5.5 A
27 38 mΩ
VGS = 10 V, ID = 6.6 A, TJ = 125 °C
36 46
gFS Forward Transconductance
VDS = 5 V, ID = 6.6 A
26 S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = 50 V, VGS = 0 V,
f = 1MHz
1118
181
7.5
0.5
1490
245
15
pF
pF
pF
Ω
Switching Characteristics
td(on)
tr
td(off)
tf
Qg(TOT)
Qg(TOT)
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = 50 V, ID = 6.6 A,
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V VDD = 50 V,
ID = 6.6 A
6.6 14
ns
1.9 10
ns
19 31 ns
2.2 10
ns
17 25 nC
8.3 12
2.6 nC
2.2 nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage VGS = 0 V, IS = 6.6 A
VGS = 0 V, IS = 1 A
(Note 2)
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
IF = 6.6 A, di/dt = 100 A/μs
0.82 1.3
0.68 1.2
40 64
36 58
V
ns
nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a) 55 °C/W when mounted on a
1 in2 pad of 2 oz copper
b) 118 °C/W when mounted on
a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. Starting TJ = 25 °C, L = 1 mH, IAS = 13 A, VDD = 90 V, VGS = 10 V.
4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
©2010 Fairchild Semiconductor Corporation
FDT86102LZ Rev. C
2
www.fairchildsemi.com


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Typical Characteristics TJ = 25 °C unless otherwise noted
40
VGS = 10 V
VGS = 4.5 V
30 VGS = 3.5 V
VGS = 3 V
20
10
0
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
1234
VDS, DRAIN TO SOURCE VOLTAGE (V)
5
Figure 1. On-Region Characteristics
5
VGS = 2.5 V
4
3
2
VGS = 3 V
VGS = 3.5 V
1
PULSE DURATION = 80 μs VGS = 4.5 V VGS = 10 V
DUTY CYCLE = 0.5% MAX
0
0 10 20 30 40
ID, DRAIN CURRENT (A)
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
2.0
1.8
ID = 6.6 A
VGS = 10 V
1.6
1.4
1.2
1.0
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On-Resistance
vs Junction Temperature
150
ID = 6.6 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
120
90
60
30
0
2
TJ = 125 oC
TJ = 25 oC
468
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs Gate to
Source Voltage
10
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
VDS = 5 V
20
TJ = 150 oC
TJ = 25 oC
10
TJ = -55 oC
0
0123
VGS, GATE TO SOURCE VOLTAGE (V)
4
Figure 5. Transfer Characteristics
40
VGS = 0 V
10
TJ = 150 oC
1
0.1
TJ = 25 oC
0.01
TJ = -55 oC
0.001
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
©2010 Fairchild Semiconductor Corporation
FDT86102LZ Rev. C
3
www.fairchildsemi.com


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Typical Characteristics TJ = 25 °C unless otherwise noted
10
ID = 6.6 A
8
6
VDD = 25 V
VDD = 50 V
4
VDD = 75 V
2
0
0 3 6 9 12 15 18
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
100
Ciss
Coss
10
f = 1 MHz
Crss
VGS = 0 V
1
0.1
1
10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. CapacitancevsDrain
to Source Voltage
20
10
TJ = 25 oC
TJ = 100 oC
1
0.001
TJ = 125 oC
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
15
12
VGS = 10 V
9
Package Limited
VGS = 4.5 V
6
3
RθJC = 12 oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
10-1
10-2
VGS = 0 V
10-3
10-4 TJ = 125 oC
10-5
10-6
10-7
TJ = 25 oC
10-8
10-9
0
5 10 15 20 25 30
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 11. Gate Leakage Current vs
Gate to Source Voltage
35
50
100 μs
10
1 ms
1
0.1
0.01
0.005
0.01
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJA = 118 oC/W
TA = 25 oC
10 ms
100 ms
1s
10 s
DC
0.1 1 10 100
VDS, DRAIN to SOURCE VOLTAGE (V)
500
Figure 12. Forward Bias Safe
Operating Area
©2010 Fairchild Semiconductor Corporation
FDT86102LZ Rev. C
4
www.fairchildsemi.com


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Typical Characteristics TJ = 25 °C unless otherwise noted
2000
1000
100
10
1
0.5
10-4
SINGLE PULSE
RθJA = 118 oC/W
TA = 25 oC
10-3
10-2
10-1
1
t, PULSE WIDTH (sec)
10
Figure 13. Single Pulse Maximum Power Dissipation
2
1 DUTY CYCLE-DESCENDING ORDER
100
1000
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
0.0005
10-4
10-3
PDM
SINGLE PULSE
RθJA = 118 oC/W
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
10
100
Figure 14. Junction-to-Ambient Transient Thermal Response Curve
1000
©2010 Fairchild Semiconductor Corporation
FDT86102LZ Rev. C
5
www.fairchildsemi.com


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6.70
6.20
0.10 C B
3.10
2.90
4
B
A
3.70
3.30
3.25
1.90
6.10
13
2.30
4.60
1.80 MAX
0.84
0.60
0.10 C B
1.90
0.95 2.30
LAND PATTERN RECOMMENDATION
SEE DETAIL A
C 0.10
0.00
GAGE
PLANE
0.08 C
7.30
6.70
NOTES: UNLESS OTHERWISE SPECIFIED
A) DRAWING BASED ON JEDEC REGISTRATION
TO-261C, VARIATION AA.
10° R0.15±0.05
R0.15±0.05
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR BURRS
DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
10°
TYP
0.35
0.20
ASME Y14.5M-2009.
E) LANDPATTERN NAME: SOT230P700X180-4BN
F) DRAWING FILENAME: MKT-MA04AREV3
0.25
SEATING
PLANE
10°
0.60 MIN
1.70
DETAIL A
SCALE: 2:1


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