Fairchild Semiconductor Electronic Components Datasheet


FDN86501LZ

MOSFET



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October 2015
FDN86501LZ
N-Channel Shielded Gate PowerTrench® MOSFET
60 V, 2.6 A, 116 mΩ
Features
General Description
„ Shielded Gate MOSFET Technology
„ Max rDS(on) = 116 mΩ at VGS = 10 V, ID = 2.6 A
„ Max rDS(on) = 173 mΩ at VGS = 4.5 V, ID = 2.1 A
„ High performance trench technology for extremely low rDS(on)
„ High power and current handling capability in a widely used
surface mount package
„ Fast switching speed
„ 100% UIL tested
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for rDS(on), switching performance and ruggedness.
Applications
„ Primary DC-DC Switch
„ Load Switch
„ RoHS Compliant
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
(Note 1b)
Ratings
60
±20
2.6
24
6
1.5
0.6
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Package Marking and Ordering Information
(Note 1)
(Note 1a)
75
80
°C/W
Device Marking
8650
Device
FDN86501LZ
Package
SSOT-3
Reel Size
7 ’’
Tape Width
8 mm
Quantity
3000 units
©2015 Fairchild Semiconductor Corporation
FDN86501LZ Rev.1.1
1
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
VDS = 48 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
On Characteristics (Note 2)
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Static Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250 μA
ID = 250 μA, referenced to 25 °C
VGS = 10 V, ID = 2.6 A
VGS = 4.5 V, ID = 2.1 A
VGS = 10 V, ID = 2.6 A, TJ = 125 °C
VDS = 10 V, ID = 2.6 A
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = 30 V, VGS = 0 V,
f = 1 MHz
Switching Characteristics
td(on)
tr
td(off)
tf
Qg
Qg
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
VDD = 30 V, ID = 2.6 A,
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V VDD = 30 V,
ID = 2.6 A
Drain-Source Diode Characteristics
VSD Source to Drain Diode Forward Voltage
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
VGS = 0 V, IS = 2.6 A
(Note 2)
IF = 2.6 A, di/dt = 100 A/μs
Min.
60
1.0
0.1
Typ.
68
1.9
-5
89
121
152
8
236
77
4.9
0.8
4.4
1.2
9.6
1.2
3.8
1.9
0.7
0.6
0.9
31
19
Max. Units
V
mVC
1 μA
±10 μA
2.4 V
mV/°C
116
173 mΩ
198
S
335 pF
110 pF
10 pF
2.0 Ω
10 ns
10 ns
20 ns
10 ns
5.4 nC
2.7 nC
nC
nC
1.3 V
50 ns
31 nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 80 °C/W when mounted on a
1 in2 pad of 2 oz copper
b) 180 °C/W when mounted on a
minimum pad.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 6 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 2 A, VDD = 60 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 9 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
©2015 Fairchild Semiconductor Corporation
FDN86501LZ Rev.1.1
2
www.fairchildsemi.com


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Typical Characteristics TJ = 25 °C unless otherwise noted.
10
VGS = 10 V
VGS = 5.5 V
8
VGS = 4.5 V
6
VGS = 3.5 V
4
2
VGS = 3 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
012345
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
5
VGS = 3 V
4
VGS = 3.5 V
3
2 VGS = 4.5 V
1
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
024
VGS = 5.5 V VGS = 10 V
6 8 10
ID, DRAIN CURRENT (A)
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
2.0
1.8
ID = 2.6 A
VGS = 10 V
1.6
1.4
1.2
1.0
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs. Junction Temperature
500
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
400
ID = 2.6 A
300
TJ = 125 oC
200
100
0
2
TJ = 25 oC
3456789
VGS, GATE TO SOURCE VOLTAGE (V)
10
Figure 4. On-Resistance vs. Gate to
Source Voltage
10
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
8
VDS = 5 V
6
4
TJ = 150 oC
TJ = 25 oC
2
TJ = -55 oC
0
1234
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
5
20
10 VGS = 0 V
1
0.1
0.01
0.0010.0
TJ = 150 oC
TJ = 25 oC
TJ = -55 oC
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
©2015 Fairchild Semiconductor Corporation
FDN86501LZ Rev.1.1
3
www.fairchildsemi.com


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Typical Characteristics TJ = 25 °C unless otherwise noted.
10
ID = 2.6 A
8
6
4
VDD = 20 V
VDD = 30 V
VDD = 40 V
2
0
01234
Qg, GATE CHARGE (nC)
1000
100
Ciss
Coss
10
Crss
f = 1 MHz
VGS = 0 V
1
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
60
Figure 7. Gate Charge Characteristics
Figure8. Capacitancevs.Drain
to Source Voltage
20
10
TJ = 25 oC
TJ = 100 oC
1
0.001
TJ = 125 oC
0.01 0.1
1
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
10-1
10-2
VDS = 0 V
10-3
10-4
10-5 TJ = 125 oC
10-6
10-7 TJ = 25 oC
10-8
10-9
10 0 6 12 18 24 30 36
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 10. Gate Leakage Current vs. Gate to Source
Voltage
50
10 10 μs
1 100 μs
THIS AREA IS
0.1 LIMITED BY rDS(on)
SINGLE PULSE
0.01 TJ = MAX RATED
RθJA = 180 oC/W
TA = 25 oC
0.001
0.1 1
CURVE BENT TO
MEASURED DATA
10
1 ms
10 ms
100 ms
1s
10 s
DC
100 300
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
1000
100
SINGLE PULSE
RθJA = 180 oC/W
TA = 25 oC
10
1
0.1
10-5 10-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2015 Fairchild Semiconductor Corporation
FDN86501LZ Rev.1.1
4
www.fairchildsemi.com


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Typical Characteristics TJ = 25 °C unless otherwise noted.
2
1 DUTY CYCLE-DESCENDING ORDER
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
SINGLE PULSE
0.0001
10-5
10-4
10-3
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
PDM
t1
t2
NOTES:
ZθJA(t)
RθJA =
=18r0(t)oCx /RWθJA
Peak TJ = PDM x ZθJA(t) + TA
Duty Cycle, D = t1 / t2
10 100
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
1000
©2015 Fairchild Semiconductor Corporation
FDN86501LZ Rev.1.1
5
www.fairchildsemi.com


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2.92±0.12
3
A 0.95
B 1.40
1.40±0.12
2.20
(0.29)
1
0.95
1.90
1.12 MAX
(0.94)
C
GAGE PLANE
0.178
0.102
0.43
0.33
(0.56)
2
0.508
0.382
0.10 M A B
1.90
1.00
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.10
0.00
0.10 M C
2.51±0.20
0.20
SEATING
PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
A) NO JEDEC REFERENCE AS OF AUGUST 2003
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR EXTRUSIONS.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M - 2009.
E) DRAWING FILE NAME: MKT-MA03BREV3
SCALE: 50:1


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