Fairchild Semiconductor Electronic Components Datasheet


FDG8850NZ

MOSFET



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April 2007
FDG8850NZ
Dual N-Channel PowerTrench® MOSFET
tm
30V,0.75A,0.4Ω
Features
„ Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A
„ Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A
„ Very low level gate drive requirements allowing operation
in 3V circuits(VGS(th) <1.5V)
„ Very small package outline SC70-6
„ RoHS Compliant
General Description
This dual N-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This device
has been designed especially for low voltage applications as
a replacement for bipolar digital transistors and small signal
MOSFETs. Since bias resistors are not required, this dual digital
FET can replace several different digital transistors, with differ-
ent bias resistor values.
G2
D1
S2
SC70-6
Pin 1
D2
G1
S1
Q1
S1
G1
Q2
D2
D1
G2
S2
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
RθJA
Thermal Resistance, Junction to Ambient Single operation
Thermal Resistance, Junction to Ambient Single operation
Package Marking and Ordering Information
Device Marking
.50
Device
FDG8850NZ
Reel Size
7”
(Note 1a)
(Note 1b)
Ratings
30
±12
0.75
2.2
0.36
0.30
–55 to +150
Units
V
V
A
W
°C
(Note 1a)
(Note 1b)
350
415
°C/W
Tape Width
8mm
Quantity
3000 units
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
1
www.fairchildsemi.com


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Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250μA, VGS = 0V
ID = 250μA, referenced to 25°C
VDS = 24V, VGS = 0V
VGS = ±12V, VDS= 0V
30
25
V
mV/°C
1 μA
±10 μA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Static Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250μA
0.65 1.0
1.5
V
ID = 250μA, referenced to 25°C
–3.0 mV/°C
VGS = 4.5V, ID = 0.75A
VGS = 2.7V, ID = 0.67A
VGS = 4.5V, ID = 0.75A ,TJ = 125°C
VDS = 5V, ID = 0.75A
0.25 0.4
0.29 0.5
0.36 0.6
3
Ω
S
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VDS = 10V, VGS = 0V, f= 1MHZ
90 120
20 30
15 25
pF
pF
pF
Switching Characteristics (note 2)
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = 5V, ID = 0.5A,
VGS = 4.5V,RGEN = 6Ω
VGS =4.5V, VDD = 5V, ID = 0.75A
4
1
9
1
1.03
0.29
0.17
10
10
18
10
1.44
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current
VSD
Source to Drain Diode Forward Voltage VGS = 0V, IS = 0.3A
(Note 2)
0.3
0.76 1.2
A
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
RθJC is guaranteed by design while RθJA is determined by the user's board design.
a. 350°C/W when mounted on a
1 in2 pad of 2 oz copper .
b. 415°C/W when mounted on a minimum pad
of 2 oz copper.
Scale 1:1 on letter size paper.
2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
2
www.fairchildsemi.com


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Typical Characteristics TJ = 25°C unless otherwise noted
2.20
VGS = 4.5V
1.76
VGS = 2.7V
VGS = 2.0V
1.32
0.88
0.44
VGS =1.8V
PULSE DURATION = 80μs
DUTY CYCLE = 0.5%MAX
VGS = 1.5V
0.00
0.0
0.5 1.0 1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
2.0
2.6
VGS = 1.8V
2.2
VGS = 2.0V
1.8
1.4 VGS = 3.5V
VGS = 2.7V
1.0
PULSE DURATION = 80μs
DUTY CYCLE = 0.5%MAX
0.6
0.00 0.44 0.88
1.32
ID, DRAIN CURRENT(A)
VGS = 4.5V
1.76 2.20
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
ID = 0.75A
1.4 VGS = 4.5V
1.2
1.0
0.8
0.6
-50
-25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On - Resistance
vs Junction Temperature
150
2.20
1.76
PULSE DURATION = 80μs
DUTY CYCLE = 0.5%MAX
1.32
VDD = 5V
0.88
TJ = 150oC
0.44
TJ = 25oC
0.00
0.0
TJ = -55oC
0.5 1.0 1.5 2.0
VGS, GATE TO SOURCE VOLTAGE (V)
2.5
Figure 5. Transfer Characteristics
0.8
ID =0.38A
PULSE DURATION = 80μs
DUTY CYCLE = 0.5%MAX
0.6
TJ = 125oC
0.4
TJ = 25oC
0.2
1234
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs Gate to
Source Voltage
2
1 VGS = 0V
5
0.1 TJ = 150oC
0.01
TJ = 25oC
1E-3
0.2
TJ = -55oC
0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
1.2
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
3
www.fairchildsemi.com


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Typical Characteristics TJ = 25°C unless otherwise noted
5
ID = 0.22A
4
200
100
3 VDD = 5V
VDD = 10V
2 VDD = 15V
10
Ciss
Coss
Crss
1
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Qg, GATE CHARGE(nC)
Figure 7. Gate Charge Characteristics
f = 1MHz
VGS = 0V
01.1 1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. CapacitancevsDrain
to Source Voltage
30
4
1
LIMITED
r DS(on)
100μs
1ms
0.1 10ms
SINGLE PULSE
0.01
TJ = MAX RATED
RθJA = 415OC/W
TA = 25OC
0.005
0.1
1
100ms
1s
DC
10 100
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
50
SINGLE PULSE
RθJA= 415OC/W
10 TA = 25OC
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
t, PULSE WIDTH (s)
Figure 10. Single Pulse Maximum Power
Dissipation
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.1
0.02
0.01
0.01 SINGLE PULSE
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
RθJA = 415oC/W
0.0001
0.001
0.01 0.1
1
t, RECTANGULAR PULSE DURATION (s)
10
Figure 11. Transient Thermal Response Curve
100 1000
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
4
www.fairchildsemi.com


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TRADEMARKS
tm
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
ACEx®
Across the board. Around the world™
ActiveArray™
Bottomless™
i-Lo
ImpliedDisconnect™
IntelliMAX™
ISOPLANAR™
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
Build it Now™
MICROCOUPLER™
QS™
TinyPower™
CoolFET™
MicroPak™
QT Optoelectronics™
TinyWire™
CROSSVOLT
MICROWIRE™
Quiet Series™
TruTranslation™
CTL™
Current Transfer Logic™
Motion-SPM™
MSX™
RapidConfigure™
RapidConnect™
µSerDes™
UHC®
DOME™
E2CMOS™
EcoSPARK®
EnSigna™
FACT Quiet Series™
FACT®
FAST®
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR®
PACMAN™
PDP-SPM™
ScalarPump™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
UniFET™
VCX™
Wire™
FASTr™
FPS™
FRFET®
GlobalOptoisolator
POP™
Power220®
Power247®
PowerEdge™
SuperSOT™-8
SyncFET™
TCM™
The Power Franchise®
GTO
HiSeC
PowerSaver™
tm
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PRODUCT STATUS DEFINITIONS
Definition of Terms
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Advance Information
Formative or In Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner
without notice.
This datasheet contains preliminary data; supplementary data will
be published at a later date. Fairchild Semiconductor reserves the
right to make changes at any time without notice to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at any time
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This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor.The datasheet is printed
for reference information only.
©2007 Fairchild Semiconductor Corporation
Rev. I26
www.fairchildsemi.com


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