Fairchild Semiconductor Electronic Components Datasheet


FDD9410_F085

MOSFET



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October 2014
FDD9410_F085
N-Channel Power Trench® MOSFET
40 V, 50 A, 4.1 mΩ
D
Features
„ Typ rDS(on) = 3.5 mΩ at VGS = 10V, ID = 50 A
„ Typ Qg(tot) = 23.5 nC at VGS = 10V, ID = 50 A
„ UIS Capability
„ RoHS Compliant
„ Qualified to AEC Q101
Applications
„ Automotive Engine Control
„ Powertrain Management
„ Solenoid and Motor Drivers
„ Integrated Starter/alternator
„ Primary Switch for 12V Systems
D
G
G
S
DTO-P-2A5K2
(TO-252)
S
For current package drawing, please refer to the Fairchild web
site  at  https://www.fairchildsemi.com/packagedrawings/TO/
TO252A03.pdf
MOSFET Maximum Ratings TJ = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGS
ID
Drain to Source Voltage
Gate to Source Voltage
Drain Current - Continuous (VGS=10) (Note 1)
Pulsed Drain Current
EAS Single Pulse Avalanche Energy
PD
Power Dissipation
Derate Above 25oC
TJ, TSTG
RθJC
RθJA
Operating and Storage Temperature
Thermal Resistance Junction to Case
Maximum Thermal Resistance Junction to Ambient
TC = 25°C
TC = 25°C
(Note 2)
(Note 3)
Ratings
40
±20
50
See Figure4
40
75
0.5
-55 to + 175
2
52
Units
V
V
A
mJ
W
W/oC
oC
oC/W
oC/W
Package Marking and Ordering Information
Device Marking
Device
Package
FDD9410
FDD9410_F085 D-PAK(TO-252)
Reel Size
13”
Tape Width
12mm
Quantity
2500 units
Notes:
1: Current is limited by bondwire configuration.
2:
3:
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the solder
maximum
©2014 Fairchild Semiconductor Corporation
FDD9410_F085 Rev. C2
1
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Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Off Characteristics
Test Conditions
Min
BVDSS Drain to Source Breakdown Voltage
IDSS Drain to Source Leakage Current
IGSS
Gate to Source Leakage Current
On Characteristics
ID = 250μA, VGS = 0V
VDS = 40V, TJ = 25oC
VGS = 0V
TJ = 175oC(Note 4)
VGS = ±20V
40
-
-
-
VGS(th)
rDS(on)
Gate to Source Threshold Voltage
Drain to Source On Resistance
Dynamic Characteristics
VGS = VDS, ID = 250μA
ID = 50A,
TJ = 25oC
VGS = 10V TJ = 175oC(Note 4)
2.0
-
-
Ciss
Coss
Crss
Rg
Qg(ToT)
Qg(th)
Qgs
Qgd
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Total Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller“ Charge
VDS = 25V, VGS = 0V,
f = 1MHz
f = 1MHz
VGS = 0 to 10V
VGS = 0 to 2V
VDD = 20V
ID = 50A
-
-
-
-
-
-
-
-
Typ
-
-
-
-
3.0
3.5
6.1
1715
453
28
2.3
23.5
3.2
9.6
4.4
Max Units
-
1
1
±100
V
μA
mA
nA
4.0 V
4.1 mΩ
7.1 mΩ
-
-
-
-
34.5
4
-
-
pF
pF
pF
Ω
nC
nC
nC
nC
Switching Characteristics
ton
td(on)
tr
td(off)
tf
toff
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Drain-Source Diode Characteristics
VDD = 20V, ID = 50A,
VGS = 10V, RGEN = 6Ω
--
- 12
- 12
- 20
-9
--
VSD Source to Drain Diode Voltage
Trr Reverse Recovery Time
Qrr Reverse Recovery Charge
ISD = 50A, VGS = 0V
ISD = 25A, VGS = 0V
IF = 50A, dISD/dt = 100A/μs,
VDD=32V
--
--
- 44
- 31.5
Note:
4: The maximum value is specified by design at TJ = 175°C. Product is not tested to this condition in production.
38
-
-
-
-
45
1.25
1.2
58
41
ns
ns
ns
ns
ns
ns
V
V
ns
nC
FDD9410_F085 Rev. C2
2
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Typical Characteristics
1.2 120
1.0
100
CURRENT LIMITED
BY PACKAGE
VGS = 10V
CURRENT LIMITED
0.8 80 BY SILICON
0.6 60
0.4 40
0.2 20
0.0
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE(oC)
Figure 1. Normalized Power Dissipation vs. Case
Temperature
2
DUTY CYCLE - DESCENDING ORDER
1
D = 0.50
0.20
0.10
0.05
0.02
0.1 0.01
SINGLE PULSE
0
25
50 75 100 125 150
TC, CASE TEMPERATURE(oC)
175
Figure 2. Maximum Continuous Drain Current vs.
Case Temperature
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TC
0.01
10-5
10-4 10-3 10-2 10-1 100
t, RECTANGULAR PULSE DURATION(s)
Figure 3. Normalized Maximum Transient Thermal Impedance
101
1000
VGS = 10V
100
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I2
175 - TC
150
SINGLE PULSE
10
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION(s)
Figure 4. Peak Current Capability
FDD9410_F085 Rev. C2
3
100 101
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Typical Characteristics
1000
100
10 100us
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(on)
1
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
0.1
1ms
10ms
100ms
1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
200
100
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
10
STARTING TJ = 150oC
0.1001
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
100
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
150
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
120 VDD = 5V
90
TJ = 175oC
60
TJ = 25oC
30
TJ = -55oC
0
3456
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
7
200
100
VGS = 0 V
10
TJ = 175 oC
1
TJ = 25 oC
0.1
0.01
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 8. Forward Diode Characteristics
150
120
90
60
80μs PULSE WIDTH
Tj=25oC
VGS
15V Top
10V
8V
7V
6V
5.5V
5V Bottom
30
5V
0
01234
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Saturation Characteristics
5
150
120
90
60
80μs PULSE WIDTH
Tj=175oC
VGS
15V5T.5oVp
10V
8V
7V
6V
5.5V
5V Bottom
30 5V
00 1 2 3 4
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 10. Saturation Characteristics
5
FDD9410_F085 Rev. C2
4
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Typical Characteristics
50
ID = 50A
40
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
30
TJ = 175oC
20
TJ = 25oC
10
0
456789
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 11. RDSON vs. Gate Voltage
10
1.8
PULSE DURATION = 80μs
1.6 DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
0.6
-80
ID = 50A
VGS = 10V
-40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE(oC)
Figure 12. Normalized RDSON vs. Junction
Temperature
1.2
VGS = VDS
1.1 ID = 250μA
1.0
0.9
0.8
0.7
0.6
-80
-40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE(oC)
Figure 13. Normalized Gate Threshold Voltage vs.
Temperature
1.10
ID = 1mA
1.05
1.00
0.95
0.90
-80
-40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
Figure 14. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
10000
1000
Ciss
Coss
100
f = 1MHz
Crss
VGS = 0V
10
0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 15. Capacitance vs. Drain to Source
Voltage
10
ID = 50A
8
6
4
VDD = 16V
VDD = 24V
VDD = 20V
2
0
0 5 10 15 20 25
Qg, GATE CHARGE(nC)
Figure 16. Gate Charge vs. Gate to Source
Voltage
FDD9410_F085 Rev. C2
5
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The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
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®
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Marking Small Speakers Sound Louder
and Better™
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MicroPak™
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MotionGrid®
MTi®
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mWSaver®
OptoHiT™
®
tm
PowerTrench®
PowerXS™
Programmable Active Droop™
QFET®
QS™
Quiet Series™
RapidConfigure™
Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
SMART START™
Solutions for Your Success™
SPM®
STEALTH™
SuperFET®
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS®
SyncFET™
Sync-Lock™
®*
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TinyBuck®
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TinyPWM™
TinyWire™
TranSiC™
TriFault Detect™
TRUECURRENT®*
μSerDes™
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仙童
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Datasheet contains the design specifications for product development. Specifications
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Rev. I71
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6
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