Fairchild Semiconductor Electronic Components Datasheet


FDD2582

MOSFET



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FDD2582
N-Channel PowerTrench® MOSFET
150V, 21A, 66m
Features
• rDS(ON) = 58m(Typ.), VGS = 10V, ID = 7A
• Qg(tot) = 19nC (Typ.), VGS = 10V
• Low Miller Charge
• Low QRR Body Diode
• UIS Capability (Single Pulse and Repetitive Pulse)
• Qualified to AEC Q101
Formerly developmental type 82855
March 2015
Applications
• DC/DC converters and Off-Line UPS
• Distributed Power Architectures and VRMs
• Primary Switch for 24V and 48V Systems
• High Voltage Synchronous Rectifier
• Direct Injection / Diesel Injection System
• 42V Automotive Load Control
• Electronic Valve Train System
DRAIN
(FLANGE)
D
GATE
SOURCE
TO-252AA
FDD SERIES
G
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (TC = 25 oC, VGS = 10V)
Continuous (TC = 100 oC, VGS = 10V)
Continuous (Tamb = 25oC, VGS = 10V, RθJA = 52oC/W)
Pulsed
Single Pulse Avalanche Energy (Note 1)
Power dissipation
Derate above 25oC
Operating and Storage Temperature
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-252
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
Ratings
150
±20
21
15
3.7
Figure 4
59
95
0.63
-55 to 175
1.58
100
52
Units
V
V
A
A
A
mJ
W
W/oC
oC
oC/W
oC/W
oC/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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Package Marking and Ordering Information
Device Marking
FDD2582
Device
FDD2582
Package
TO-252AA
Reel Size
330mm
Tape Width
16mm
Quantity
2500 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 120V
VGS = 0V
TC = 150oC
VGS = ±20V
150
-
-
-
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
rDS(ON)
Drain to Source On Resistance
VGS = VDS, ID = 250µA
ID = 7A, VGS = 10V
ID = 4A, VGS = 6V,
ID = 7A, VGS = 10V,
TC = 175oC
2
-
-
-
Dynamic Characteristics
CISS
COSS
CRSS
Qg(TOT)
Qg(TH)
Qgs
Qgs2
Qgd
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
VDS = 25V, VGS = 0V,
f = 1MHz
VGS = 0V to 10V
VGS = 0V to 2V
VDD = 75V
ID = 7A
Ig = 1.0mA
-
-
-
-
-
-
-
-
Resistive Switching Characteristics (VGS = 10V)
tON
td(ON)
Turn-On T ime
Turn-On Delay Time
tr
td(OFF)
Rise Time
Turn-Off Delay Time
VDD = 75V, ID = 7A
VGS = 10V, RGS = 16
tf Fall Time
tOFF
Turn-Off Time
-
-
-
-
-
-
Drain-Source Diode Characteristics
VSD Source to Drain Diode Voltage
trr
QRR
Reverse Recovery Time
Reverse Recovered Charge
Notes:
1: Starting TJ = 25°C, L = 1.17 mH, IAS = 10A.
ISD = 7A
ISD = 4A
ISD = 7A, dISD/dt = 100A/µs
ISD = 7A, dISD/dt = 100A/µs
-
-
-
-
Typ Max Units
- -V
-
-
1
250
µA
- ±100 nA
-
0.058
0.066
0.151
4
0.066
0.099
0.172
V
1295
145
30
19
2.4
6.2
3.8
4.2
-
-
-
25
3.2
-
-
-
pF
pF
pF
nC
nC
nC
nC
nC
- 41 ns
8 - ns
19 - ns
32 - ns
19 - ns
- 77 ns
- 1.25 V
- 1.0 V
- 67 ns
- 134 nC
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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Typical Characteristics TC = 25°C unless otherwise noted
1.2 25
VGS = 10V
1.0
20
0.8
15
0.6
10
0.4
0.2 5
0
0 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
0
25
50 75 100 125 150
TC, CASE TEMPERATURE (oC)
175
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
10-5
PDM
SINGLE PULSE
10-4
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
Figure 3. Normalized Maximum Transient Thermal Impedance
101
300
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
VGS = 10V
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
175 - TC
150
20
10-5
10-4
10-3
10-2
10-1
t , PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
100 101
FDD2582 Rev. 1.2


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Typical Characteristics TC = 25°C unless otherwise noted
200 100
100
10µs
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
100µs
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10 1ms
OPERATION IN THIS
AREA MAY BE
1 LIMITED BY rDS(ON)
10ms
0.1
1
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
DC
10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
300
Figure 5. Forward Bias Safe Operating Area
10 STARTING TJ = 25oC
1
0.001
STARTING TJ = 150oC
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
10
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
40 VDD = 15V
30
20
TJ = 25oC
10
TJ = 175oC
TJ = -55oC
50
VGS = 10V
40 PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
30
20
10
VGS = 7V
VGS = 6V
VGS = 5V
0
3.5
4.0 4.5 5.0 5.5 6.0 6.5
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
7.0
90
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
80
VGS = 6V
70
60 VGS = 10V
50
0
5 10 15 20
ID, DRAIN CURRENT (A)
25
Figure 9. Drain to Source On Resistance vs Drain
Current
0
0
1234
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Saturation Characteristics
5
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
2.0
1.5
1.0
0.5
-80
VGS = 10V, ID = 21A
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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Typical Characteristics TC = 25°C unless otherwise noted
1.2 1.2
VGS = VDS, ID = 250µA
ID = 250µA
1.0
1.1
0.8
1.0
0.6
0.4
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
0.9
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
2000
1000
COSS CDS + CGD
100 CRSS = CGD
CISS = CGS + CGD
10
VDD = 75V
8
6
4
VGS = 0V, f = 1MHz
10
0.1 1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
150
Figure 13. Capacitance vs Drain to Source
Voltage
2
0
0
WAVEFORMS IN
DESCENDING ORDER:
ID = 21A
ID = 7A
5 10 15
Qg, GATE CHARGE (nC)
20
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01
0
tP
IAS
BVDSS
VDS
VDD
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VGS
Ig(REF)
VDS
L
DUT
+
VDD
-
Figure 17. Gate Charge Test Circuit
VDD
Qg(TOT)
VDS
VGS
VGS = 2V
0
Qg(TH)
Qgs2
Qgs
Ig(REF)
0
Qgd
VGS = 10V
Figure 18. Gate Charge Waveforms
VDS
RL
VGS
VGS
RGS
DUT
+
VDD
-
Figure 19. Switching Time Test Circuit
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
Figure 20. Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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Thermal Resistance vs. Mounting Pad Area
The max imum r ated j unction t emperature, T JM, an d t he
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. T herefore t he a pplication’s amb ient
temperature, TA (oC), an d t hermal resistance R θJA (oC/W)
must be reviewed to en sure t hat T JM is ne ver ex ceeded.
Equation 1 ma thematically represents the relationship and
serves as the basis for establishing the rating of the part.
125
100
75
PDM
=
-(--T---J---M-------–-----T---A-----)
Rθ JA
(EQ. 1)
50
RθJA = 33.32+ 23.84/(0.268+Area) EQ.2
RθJA = 33.32+ 154/(1.73+Area) EQ.3
In us ing su rface mount de vices suc h as t he TO-252
package, the environment in which it is applied will have a
significant in fluence o n t he p art’s cur rent and max imum
power d issipation ratings. Precise d etermination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. T he number o f co pper la yers and t he t hickness of t he
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. F or no n s teady st ate ap plications, t he pu lse w idth, t he
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild p rovides t hermal information to as sist t he
designer’s preliminary ap plication ev aluation. F igure 21
defines t he R θJA f or t he de vice as a f unction of t he t op
copper ( component si de) ar ea. T his is f or a h orizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction t emperature o r p ower di ssipation. P ulse
applications ca n be ev aluated us ing t he F airchild device
Spice t hermal model or m anually u tilizing t he no rmalized
maximum transient thermal impedance curve.
Thermal resistances co rresponding to ot her co pper areas
can be obtained f rom F igure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in in ches s quare a nd eq uation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
Rθ JA = 33.32 + (---0---.--2---6--28---3--+-.-8---A4----r---e---a---)
(EQ. 2)
Area in Inches Squared
Rθ JA = 33.32 + (---1---.-7---3---1--+-5---4-A----r---e---a---)
(EQ. 3)
Area in Centimeters Squared
25
0.01
(0.0645)
0.1
(0.645)
1
(6.45)
10
(64.5)
AREA, TOP COPPER AREA in2 (cm2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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PSPICE Electrical Model
.SUBCKT FDD2582 2 1 3 ;
Ca 12 8 4e-10
Cb 15 14 4.6e-10
Cin 6 8 1.24e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 160.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 4.88e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.24e-9
RLgate 1 9 48.8
RLdrain 2 5 10
RLsource 3 7 22.4
rev July 2002
GATE
1
DPLCAP 5
10
RSLC2
RSLC1
51
5
51
ESLC
DBREAK
11
LDRAIN
DRAIN
2
RLDRAIN
LGATE
RLGATE
-
ESG
6
8
+ EVTHRES
EVTEMP
+ 19 -
8
RGATE + 18 - 6
9 20 22
CIN
S1A
12 13
8
S2A
14
13
15
50
RDRAIN
16
21
+
17
EBREAK 18
-
MWEAK
DBODY
MMED
MSTRO
87
RSOURCE
LSOURCE
SOURCE
3
RLSOURCE
RBREAK
17 18
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 37e-3
Rgate 9 20 1.8
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 11.9e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
S1B S2B
CA
13 CB
+ + 14
EGS
6
8
-
EDS
5
8
-
RVTEMP
19
IT -
VBAT
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*42),2.5))}
.MODEL DbodyMOD D (IS=2.3E-12 RS=5.3e-3 TRS1=2.2e-3 TRS2=4.5e-7
+ CJO=8.8e-10 M=0.64 TT=3.8e-8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.4 TRS1=1.4e-3 TRS2=-5e-5)
.MODEL DplcapMOD D (CJO=2.75e-10 IS=1.0e-30 N=10 M=0.67)
.MODEL MmedMOD NMOS (VTO=3.76 KP=2.7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.64)
.MODEL MstroMOD NMOS (VTO=4.25 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.2 KP=0.068 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=16.4 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1.1e-8)
.MODEL RdrainMOD RES (TC1=1.0e-2 TC2=2.6e-5)
.MODEL RSLCMOD RES (TC1=2.7e-3 TC2=2.0e-6)
.MODEL RsourceMOD RES (TC1=1.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.7e-5)
.MODEL RvtempMOD RES (TC1=-3.7e-3 TC2=1.9e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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SABER Electrical Model
REV July 2002
ttemplate FDD2582 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.3e-12,rs=5.3e-3,trs1=2.2e-3,trs2=4.5e-7,cjo=8.8e-10,m=0.64,tt=3.8e-8,xti=4.2)
dp..model dbreakmod = (rs=0.4,trs1=1.4e-3,trs2=-5.0e-5)
dp..model dplcapmod = (cjo=2.75e-10,isl=10.0e-30,nl=10,m=0.67)
m..model mmedmod = (type=_n,vto=3.76,kp=2.7,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.25,kp=30,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.2,kp=0.068,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-5.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3)
DPLCAP 5
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4) 10
c.ca n12 n8 = 4e-10
RSLC1
c.cb n15 n14 = 4.6e-10
c.cin n6 n8 = 1.24e-9
RSLC2
51
ISCL
LDRAIN
RLDRAIN
DRAIN
2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 160.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
GATE
1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
LGATE
RLGATE
-
ESG
6
8
+
EVTEMP
RGATE + 18 -
9 20 22
6
EVTHRES
+ 19 -
8
CIN
50
RDRAIN
16
21
DBREAK
11
MWEAK
MMED
MSTRO
8
EBREAK
+
17
18
-
7
RSOURCE
DBODY
LSOURCE
SOURCE
3
RLSOURCE
l.lgate n1 n9 = 4.88e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.24e-9
S1A
12 13
8
S1B
S2A
14
13
S2B
15
RBREAK
17 18
RVTEMP
res.rlgate n1 n9 = 48.8
res.rldrain n2 n5 = 10
13
CA
+
res.rlsource n3 n7 = 22.4
EGS
6
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
-
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
CB
+ 14
EDS
5
8
-
19
IT -
VBAT
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1.1e-8
res.rdrain n50 n16 = 37e-3, tc1=1.0e-2,tc2=2.6e-5
res.rgate n9 n20 = 1.8
res.rslc1 n5 n51 = 1.0e-6, tc1=2.7e-3,tc2=2.0e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 11.9e-3, tc1=1.0e-3,tc2=1.0e-6
res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.7e-5
res.rvtemp n18 n19 = 1, tc1=-3.7e-3,tc2=1.9e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/42))** 2.5))
}
}
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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SPICE Thermal Model
REV 19 July 2002
FDD2582
CTHERM1 TH 6 1.6e-3
CTHERM2 6 5 4.5e-3
CTHERM3 5 4 5.0e-3
CTHERM4 4 3 8.0e-3
CTHERM5 3 2 8.2e-3
CTHERM6 2 TL 4.7e-2
RTHERM1 TH 6 3.3e-2
RTHERM2 6 5 7.9e-2
RTHERM3 5 4 9.5e-2
RTHERM4 4 3 1.4e-1
RTHERM5 3 2 2.9e-1
RTHERM6 2 TL 6.7e-1
SABER Thermal Model
SABER thermal model FDD2582
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.6e-3
ctherm.ctherm2 6 5 =4.5e-3
ctherm.ctherm3 5 4 =5.0e-3
ctherm.ctherm4 4 3 =8.0e-3
ctherm.ctherm5 3 2 =8.2e-3
ctherm.ctherm6 2 tl =4.7e-2
rrtherm.rtherm1 th 6 =3.3e-2
rtherm.rtherm2 6 5 =7.9e-2
rtherm.rtherm3 5 4 =9.5e-2
rtherm.rtherm4 4 3 =1.4e-1
rtherm.rtherm5 3 2 =2.9e-1
rtherm.rtherm6 2 tl =6.7e-1
}
th JUNCTION
RTHERM1
RTHERM2
6
5
RTHERM3
RTHERM4
4
RTHERM5
3
RTHERM6
2
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
tl CASE
©2002 Fairchild Semiconductor Corporation
FDD2582 Rev. 1.2


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