Analog Devices Semiconductor Electronic Components Datasheet


ADM2481

Isolated RS-485 Transceiver



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Data Sheet
FEATURES
RS-485 transceiver with electrical data isolation
Complies with ANSI TIA/EIA-485-A and ISO 8482: 1987(E)
500 kbps data rate
Slew rate-limited driver outputs
Low power operation: 2.5 mA maximum
Suitable for 5 V or 3.3 V operations (VDD1)
High common-mode transient immunity: >25 kV/μs
True fail-safe receiver inputs
Chatter-free power-up/power-down protection
256 nodes on bus
Thermal shutdown protection
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per
UL 1577
VDE certificates of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak
Operating temperature range: −40°C to +85°C
APPLICATIONS
Low power RS-485/RS-422 networks
Isolated interfaces
Building control networks
Multipoint data transmission systems
GENERAL DESCRIPTION
The ADM2481 differential bus transceiver is an integrated,
galvanically isolated component designed for bidirectional data
communication on balanced, multipoint bus transmission lines.
It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).
Using iCoupler® technology from Analog Devices, Inc., the
ADM2481 combines a 3-channel isolator, a three-state diffe-
rential line driver, and a differential input receiver into a single
package. The logic side of the device is powered with either a
5 V or 3 V supply, and the bus side uses a 5 V supply only.
The ADM2481 is slew-limited to reduce reflections with improp-
erly terminated transmission lines. The controlled slew rate
limits the data rate to 500 kbps. The input impedance of the
device is 96 kΩ, allowing up to 256 transceivers on the bus. Its
driver has an active-high enable feature. The driver differential
outputs and receiver differential inputs are connected internally
Half-Duplex, iCoupler
Isolated RS-485 Transceiver
ADM2481
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
ADM2481
DE
TxD
RxD
RE
GND1
GND2
Figure 1.
A
B
to form a differential I/O port. When the driver is disabled or
when VDD1 or VDD2 = 0 V, this imposes minimal loading on
the bus. An active-high receiver disable feature, which causes
the receiver output to enter a high impedance state, is provided
as well.
The receiver inputs have a true fail-safe feature that ensures a
logic-high receiver output level when the inputs are open or
shorted. This guarantees that the receiver outputs are in a
known state before communication begins and at the point
when communication ends.
Current limiting and thermal shutdown features protect against
output short circuits and bus contention situations that might
cause excessive power dissipation. The part is fully specified
over the industrial temperature range of −40°C to +85°C and is
available in a 16-lead, wide body SOIC package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.


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ADM2481* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• ADM2481 Evaluation Board
Documentation
Application Notes
• AN-1176: Component Footprints and Symbols in the
Binary .Bxl File Format
• AN-1179: Junction Temperature Calculation for Analog
Devices RS-485/RS-422, CAN, and LVDS/M-LVDS
Transceivers
• AN-960: RS-485/RS-422 Circuit Implementation Guide
Data Sheet
• ADM2481: Half-Duplex, iCouplerIsolated RS-485
Transceiver
User Guides
• UG-316: Evaluation Board for the ADM2481 2.5 kV Signal
Isolated, 500 kbps, Half-Duplex RS-485 Transceiver
Reference Materials
Solutions Bulletins & Brochures
• Emerging Energy Applications Solutions Bulletin, Volume
10, Issue 4
• Test & Instrumentation Solutions Bulletin, Volume 10,
Issue 3
Technical Articles
• MS-2127: Designing with iCoupler Digital Isolators in
Solar PV Inverters
Design Resources
• ADM2481 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
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ADM2481
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 4
Regulatory Information ............................................................... 4
Insulation and Safety-Related Specifications............................ 4
VDE 0884 Insulation Characteristics ........................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
6/12—Rev. 0 to Rev. A
Updated Safety and Regulatory Approvals (Throughout) .......... 1
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
7/10—Revision 0: Initial Version
Data Sheet
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 11
Switching Characteristics .............................................................. 12
Circuit Description......................................................................... 13
Electrical Isolation...................................................................... 13
Truth Tables................................................................................. 14
Thermal Shutdown .................................................................... 14
True Fail-Safe Receiver Inputs .................................................. 14
Magnetic Field Immunity.......................................................... 14
Applications Information .............................................................. 16
Printed Circuit Board (PCB) Layout ....................................... 16
Isolated Power Supply Circuit .................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
Rev. A | Page 2 of 20


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Data Sheet
ADM2481
SPECIFICATIONS
3.0 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DRIVER
Differential Outputs
Differential Output Voltage
Δ |VOD| for Complementary Output States
Common-Mode Output Voltage
Δ |VOC| for Complementary Output States
Output Short-Circuit Current,
VOUT = High
VOUT = Low
Logic Inputs
Input High Voltage
Input Low Voltage
CMOS Logic Input Current (TxD, DE, RE)
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Input Hysteresis
Input Resistance (A, B)
Input Current (A, B)
RxD Logic Output
Output High Voltage
Output Low Voltage
Output Short-Circuit Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
Logic Side
Bus Side
COMMON-MODE TRANSIENT IMMUNITY1
Symbol Min
Typ Max Unit Test Conditions/Comments
VOD 2.0
VOD 1.5
VOD3
1.5
VOC
ISC
−250
−250
5
5
5
5
0.2
3
0.2
+250
+250
V RL = ∞, see Figure 16
V RL = 50 Ω (RS-422), see Figure 16
V RL = 27 Ω (RS-485), see Figure 16
V VTEST = −7 V to +12 V, VDD1 ≥ 4.75,
see Figure 17
V RL = 27 Ω or 50 Ω, see Figure 16
V RL = 27 Ω or 50 Ω, see Figure 16
V RL = 27 Ω or 50 Ω, see Figure 16
mA −7 V ≤ VOUT ≤ +12 V
mA −7 V ≤ VOUT ≤ +12 V
VIH 0.7 VDD1
V TxD, DE, RE
VIL
0.25 VDD1 V
TxD, DE, RE
II
−10
+0.01 +10
μA TxD, DE, RE = VDD1 or 0 V
VTH
−200
−125 −30
mV −7 V ≤ VCM ≤ +12 V
VHYS 20 mV −7 V ≤ VCM ≤ +12 V
96 150
kΩ −7 V ≤ VCM ≤ +12 V
0.125 mA VIN = 12 V
−0.1 mA VIN = −7 V
VOH VDD1 − 0.1
V IOUT = 20 μA, VA − VB = 0.2 V
VDD1 − 0.4 VDD1 − 0.2
V IOUT = 4 mA, VA − VB = 0.2 V
VOL 0.1 V IOUT = −20 μA, VA − VB = −0.2 V
0.4 V IOUT = −4 mA, VA − VB = −0.2 V
ISC 7
85 mA VOUT = GND or VCC
±1 μA 0.4 V ≤ VOUT ≤ 2.4 V
IDD1
IDD2
VCM 25
2.5 mA 4.5 V ≤ VDD1 ≤ 5.5 V, outputs
unloaded, RE = 0 V
1.3 mA 3.0 V ≤ VDD1 ≤ 3.6 V, outputs
unloaded, RE = 0 V
2.0 mA Outputs unloaded, DE = 5 V
1.7 mA Outputs unloaded, DE = 0 V
kV/μs TxD = VDD1 or 0 V, VCM = 1 kV,
transient magnitude = 800 V
1 Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation.
VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The
common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 3 of 20


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ADM2481
Data Sheet
TIMING SPECIFICATIONS
3.0 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay
Skew
Rise/Fall Time
Enable Time
Disable Time
RECEIVER
Propagation Delay
Differential Skew
Enable Time
Disable Time
Symbol
tPLH, tPHL
tSKEW
tR, tF
tPLH, tPHL
tSKEW
Min Typ Max Unit
500 kbps
250 620 ns
40 ns
200 600 ns
1050 ns
1050 ns
400
25
40
1050
250
70
70
ns
ns
ns
ns
Test Conditions/Comments
RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22
RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22
RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22
RL = 500 Ω, CL = 100 pF, see Figure 19 and Figure 24
RL = 500 Ω, CL = 15 pF, see Figure 19 and Figure 24
CL = 15 pF, see Figure 20 and Figure 23
CL = 15 pF, see Figure 20 and Figure 23
RL = 1 kΩ, CL = 15 pF, see Figure 21 and Figure 25
RL = 1 kΩ, CL = 15 pF, see Figure 21 and Figure 25
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input-Output)1
Capacitance (Input-Output)1
Input Capacitance2
Symbol
RI-O
CI-O
CI
Min Typ
1012
3
4
Max Unit
pF
pF
Test Conditions
f = 1 MHz
1 Device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
Table 4. ADM2481 Approvals
Organization Approval Type
UL Recognized under the Component Recognition
Program of Underwriters Laboratories, Inc.
VDE Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-12
Notes
In accordance with UL 1577, each ADM2481 is proof tested by
applying an insulation test voltage of ≥ 3000 V rms for 1 second
(current leakage detection limit = 5 µA).
In accordance with DIN V VDE V 0884-10, each ADM2481 is proof
tested by applying an insulation test voltage of ≥ 1050 V peak for
1 second (partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
2500
7.7
Minimum External Tracking (Creepage)
L(I02)
7.6
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>175
IIIa
Unit
V rms
mm
mm
mm
V
Conditions
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (Table 1 in DIN VDE 0110,1/89)
Rev. A | Page 4 of 20


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Data Sheet
ADM2481
VDE 0884 INSULATION CHARACTERISTICS
This isolator is suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by
means of protective circuits.
Table 6.
Description
Installation Classification per DIN VDE 0110 for Rated Mains Voltage
≤150 V rms
≤300 V rms
≤400 V rms
Climatic Classification
Pollution Degree (Table 1 in DIN VDE 0110)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
VIORM × 1.875 = VPR, 100% Production Tested
tm = 1 sec, Partial Discharge of < 5 pC
Input-to-Output Test Voltage, Method a
(After Environmental Tests, Subgroup 1)
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge of < 5 pC
(After Input and/or Safety Test, Subgroup 2/3)
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge of < 5 pC
Highest Allowable Overvoltage
(Transient Overvoltage, tTR = 10 sec)
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; see Figure 13)
Case Temperature
Input Current
Output Current
Insulation Resistance at TS, VIO = 500 V
Symbol
VIORM
VPR
VPR
VTR
TS
IS, INPUT
IS, OUTPUT
RS
Characteristic Unit
I to IV
I to III
I to II
40/85/21
2
560
1050
VPEAK
VPEAK
896
672
4000
150
265
335
>109
VPEAK
VPEAK
VPEAK
°C
mA
mA
Rev. A | Page 5 of 20


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ADM2481
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 7.
Parameter
VDD1
VDD2
Digital Input Voltage (DE, RE, TxD)
Digital Output Voltage (RxD)
Driver Output/Receiver Input Voltage
ESD Rating: Contact (Human Body
Model) (A, B Pins)
Operating Temperature Range
Storage Temperature Range
Average Output Current per Pin
θJA Thermal Impedance
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.5 V to +7 V
−0.5 V to +6 V
−0.5 V to VDD1 + 0.5 V
−0.5 V to VDD1 + 0.5 V
−9 V to +14 V
±2 kV
−40°C to +85°C
−55°C to +150°C
−35 mA to +35 mA
65°C/W
260°C
215°C
220°C
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 20


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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM2481
VDD1 1
16 VDD2
GND11 2
15 GND21
RxD 3 ADM2481 14 NC
RE 4 TOP VIEW 13 B
DE 5 (Not to Scale) 12 A
TxD 6
11 NC
GND11 7
GND11 8
10 GND21
9 GND21
NC = NO CONNECT
1 PIN 2, PIN 7, AND PIN 8 MUST BE CONNECTED TO GND1.
PIN 9, PIN 10, AND PIN 15 MUST BE CONNECTED TO GND2.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
1 VDD1
2, 7, 8
GND1
3 RxD
4 RE
5
6
9, 10, 15
11, 14
12
DE
TxD
GND2
NC
A
13 B
16 VDD2
Description
Power Supply (Logic Side).
Ground (Logic Side).
Receiver Output Data. When enabled, if (A − B) ≥ −30 mV, then RxD = high; if (A − B) ≤ −200 mV, then
RxD = low. This is a tristate output when the receiver is disabled, that is, when RE is driven high.
Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and
driving it high disables the receiver.
Driver Enable Input. Driving the input high enables the driver, and driving it low disables the driver.
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground (Bus Side).
No Connect.
Noninverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is
powered down, Pin A is put into a high impedance state to avoid overloading the bus.
Inverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered
down, Pin B is put into a high impedance state to avoid overloading the bus.
Power Supply (Bus Side).
Rev. A | Page 7 of 20


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ADM2481
TYPICAL PERFORMANCE CHARACTERISTICS
1.6
IDD1_RCVR_ENABLE @ 5.5V
1.4
1.2
1.0
0.8
IDD2_DE_ENABLE @ 5.5V
0.6
0.4
0.2
0
–40
25
85
TEMPERATURE (°C)
Figure 3. Unloaded Supply Current vs. Temperature
120
100
80
60
40
20
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
Figure 4. Output Current vs. Driver Output Low Voltage
–10
–30
–50
–70
–90
–110
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
Figure 5. Output Current vs. Driver Output High Voltage
Data Sheet
0.32
0.30
0.28
0.26
0.24
0.22
0.20
–40 –25 –10
5
20 35 50 65 80
TEMPERATURE (°C)
Figure 6. Receiver Output Low Voltage vs. Temperature, IOUT = –4 mA
4.78
4.76
4.74
4.72
4.70
4.68
4.66
–40 –25 –10
5
20 35 50 65 80
TEMPERATURE (°C)
Figure 7. Receiver Output High Voltage vs. Temperature, IOUT = 4 mA
90
80
70
60
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
Figure 8. Driver Output Current vs. Differential Output Voltage
Rev. A | Page 8 of 20


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Data Sheet
600
500
400
300 tPLHA
tPHLA
tPLHB
200 tPHLB
100
0
–40 –15 10 35 60
TEMPERATURE (°C)
Figure 9. Driver Propagation Delay vs. Temperature
85
800
700
tPHL
600
tPLH
500
400
300
200
100
0
–40 –15 10 35 60
TEMPERATURE (°C)
Figure 10. Receiver Propagation Delay vs. Temperature
85
ADM2481
1
2
4
CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V
M200ns
A CH1 3.10V
T 1.33600µs
Figure 11. Driver/Receiver Propagation Delay, High to Low
1
2
4
CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V
M200ns
A CH1 3.10V
T 360.000ns
Figure 12. Driver/Receiver Propagation Delay, Low to High
Rev. A | Page 9 of 20


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ADM2481
350
300
250
BUS SIDE
200
150
LOGIC SIDE
100
50
0
0 50 100 150 200
CASE TEMPERATURE (°C)
Figure 13. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per VDE 0884
35
30
25
20
15
10
5
0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25
OUTPUT VOLTAGE (V)
Figure 14. Output Current vs. Receiver Output Low Voltage
Data Sheet
0
–5
–10
–15
–20
–25
–30
3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
OUTPUT VOLTAGE (V)
Figure 15. Output Current vs. Receiver Output High Voltage
Rev. A | Page 10 of 20


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Data Sheet
TEST CIRCUITS
VOD
RL
RL
VOC
Figure 16. Driver Voltage Measurement
ADM2481
0V OR 3V
DE IN
A
DE
B
S1
RL
CL
VOUT
Figure 19. Driver Enable/Disable
VCC
S2
375
VOD3
60
375
VTEST
Figure 17. Driver Voltage Measurement over Common-Mode Range
A
B RE
VOUT
CL
Figure 20. Receiver Propagation Delay
A
RL
B
CL1
CL2
Figure 18. Driver Propagation Delay
+1.5V
–1.5V
S1
RE IN
RL
RE
CL
VOUT
Figure 21. Receiver Enable/Disable
VCC
S2
Rev. A | Page 11 of 20


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ADM2481
SWITCHING CHARACTERISTICS
VDD1
0.5VDD1
0V tPLH
B
1/2VOD
VOD
0.5VDD1
tPHL
A
VOH
A, B
VOL
90% POINT
10% POINT
tR
tSKEW = |tPLH tPHL|
90% POINT
10% POINT
tF
Figure 22. Driver Propagation Delay, Rise/Fall Timing
A–B
RxD
0V 0V
tPLH
tPHL
1.5V tSKEW = |tPLH tPHL|
1.5V
Figure 23. Receiver Propagation Delay
VOH
VOL
Data Sheet
DE 0.5VDD1
tZL
0.5VDD1
tLZ
0.7VDD1
0.3VDD1
A, B
A, B
2.3V
tZH
2.3V
VOL + 0.5V
tHZ
VOH – 0.5V
Figure 24. Driver Enable/Disable Timing
VOL
VOH
0V
RE 0.5VDD1
tZL
0.5VDD1
tLZ
0.7VDD1
0.3VDD1
RxD
RxD
1.5V
OUTPUT LOW
VOL + 0.5V
VOL
tZH tHZ
OUTPUT HIGH
1.5V
VOH – 0.5V
VOH
0V
Figure 25. Receiver Enable/Disable Timing
Rev. A | Page 12 of 20


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Data Sheet
ADM2481
CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2481, electrical isolation is implemented on the
logic side of the interface. Therefore, the part has two main
sections: a digital isolation section and a transceiver section (see
Figure 26). Driver input and data enable signals, applied to the
TxD and DE pins, respectively, and referenced to logic ground
(GND1), are coupled across an isolation barrier to appear at the
transceiver section referenced to isolated ground (GND2).
Similarly, the receiver output, referenced to isolated ground in
the transceiver section, is coupled across the isolation barrier
to appear at the RxD pin referenced to logic ground (GND1).
iCoupler Technology
The digital signals are transmitted across the isolation barrier
using iCoupler technology. This technique uses chip-scale
transformer windings to couple the digital signals magnet-
ically from one side of the barrier to the other. Digital inputs
are encoded into waveforms that are capable of exciting the
primary transformer winding. At the secondary winding, the
induced waveforms are then decoded into the binary value that
was originally transmitted.
VDD1
VDD2
ISOLATION
BARRIER
A
TxD
ENCODE
DECODE
D
B
DE
ENCODE
DECODE
RxD
DECODE
ENCODE
R
RE
DIGITAL ISOLATION
TRANSCEIVER
GND1
GND2
Figure 26. Digital Isolation and Transceiver Sections
Rev. A | Page 13 of 20


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ADM2481
TRUTH TABLES
The following truth tables use the abbreviations shown in Table 9.
Table 9.
Letter
H
L
X
Z
NC
Description
High level
Low level
Don’t care
High impedance (off )
Disconnected
Table 10. Transmitting
Supply Status
VDD1
VDD2
DE
On On H
On On H
On On L
On Off X
Off On L
Off Off X
Inputs
TxD
H
L
X
X
L
X
Outputs
AB
HL
LH
ZZ
ZZ
ZZ
ZZ
Table 11. Receiving
Supply Status
Inputs
VDD1
VDD2
A − B (V)
On On >−0.03
On On <−0.2
On On −0.2 < A − B < −0.03
On On Inputs open
On On X
On Off X
Off Off X
RE
L or NC
L or NC
L or NC
L or NC
H
L or NC
L or NC
Outputs
RxD
H
L
Indeterminate
H
Z
H
L
THERMAL SHUTDOWN
The ADM2481 contains thermal shutdown circuitry that
protects the part from excessive power dissipation during
fault conditions. Shorting the driver outputs to a low impedance
source can result in high driver currents. The thermal sensing
circuitry detects the increase in die temperature under this
condition and disables the driver outputs. This circuitry is
designed to disable the driver outputs when a die temperature
of 150°C is reached. As the device cools, the drivers are re-enabled
at a temperature of 140°C.
Data Sheet
TRUE FAIL-SAFE RECEIVER INPUTS
The receiver inputs have a true fail-safe feature that ensures that
the receiver output is high when the inputs are open or shorted.
During line-idle conditions, when no driver on the bus is
enabled, the voltage across a terminating resistance at the
receiver input decays to 0 V. With traditional transceivers,
receiver input thresholds specified between −200 mV and
+200 mV mean that external bias resistors are required on the
A and B pins to ensure that the receiver outputs are in a known
state. The true fail-safe receiver input feature eliminates the
need for bias resistors by specifying the receiver input thresh-
old between −30 mV and −200 mV. The guaranteed negative
threshold means that when the voltage between A and B decays
to 0 V, the receiver output is guaranteed to be high.
MAGNETIC FIELD IMMUNITY
Because iCouplers use a coreless technology, no magnetic
components are present, and the problem of magnetic satura-
tion of the core material does not exist. Therefore, iCouplers
have essentially infinite dc field immunity. The analysis that
follows defines the conditions under which this might occur.
The 3 V operating condition of the ADM2481 is examined
because it represents the most susceptible mode of operation.
The limitation on the ac magnetic field immunity of the
iCoupler is set by the condition in which the induced error
voltage in the receiving coil (the bottom coil in this case) is
made sufficiently large, either to falsely set or reset the decoder.
The voltage induced across the bottom coil is given by
V
=

dt

πrn2
;
n = 1, 2, ... , N
where, if the pulses at the transformer output are greater than
1.0 V in amplitude:
β is the magnetic flux density (gauss).
N is the number of turns in receiving coil.
rn is the radius of nth turn in receiving coil (cm).
The decoder has a sensing threshold of about 0.5 V; therefore,
there is a 0.5 V margin in which induced voltages can be
tolerated.
Rev. A | Page 14 of 20


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Data Sheet
Given the geometry of the receiving coil and an imposed
requirement that the induced voltage is, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated, as shown in Figure 27.
100.000
10.000
1.000
0.100
0.010
0.001
1k
10k 100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kGauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
and is the worst-case polarity, it reduces the received pulse from
>1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold
of the decoder.
ADM2481
These magnetic flux density values are shown in Figure 28,
using more familiar quantities such as maximum allowable
current flow, at given distances away from the ADM2481
transformers.
1000.00
100.00
DISTANCE = 1m
DISTANCE = 5mm
10.00
1.00
DISTANCE = 100mm
0.10
0.01
1k
10k 100k 1M 10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 28. Maximum Allowable Current for Various
Current-to-ADM2481 Spacings
100M
At combinations of strong magnetic field and high frequency,
any loops formed by printed circuit board traces could induce
large enough error voltages to trigger the thresholds of succeed-
ing circuitry. To avoid this possibility, take care in the layout of
such traces.
Rev. A | Page 15 of 20


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ADM2481
Data Sheet
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADM2481 signal isolated RS-485 transceiver requires no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 29).
Bypass capacitors are most conveniently connected between
Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for
VDD2. The capacitor value must be between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and
the input power supply pin must not exceed 20 mm.
VDD1
GND1
RxD
RE
DE
TxD
GND1
GND1
ADM2481
NC = NO CONNECT
VDD2
GND2
NC
B
A
NC
GND2
GND2
Figure 29. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, take
care to ensure that board coupling across the isolation barrier
is minimized. Furthermore, the board layout must be designed
such that any coupling that does occur equally affects all pins
on a given component side.
Failure to ensure this can cause voltage differentials between
pins that exceed the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
ISOLATED POWER SUPPLY CIRCUIT
The ADM2481 requires isolated power capable of 5 V at
100 mA to be supplied between the VDD2 and GND2 pins. If
no suitable integrated power supply is available, a discrete
circuit, such as the one in Figure 30, can be used. A center-
tapped transformer provides electrical isolation. The primary
winding is excited with a pair of square waveforms that are 180°
out of phase with each other. A pair of Schottky diodes and a
smoothing capacitor are used to create a rectified signal from
the secondary winding. The ADP3330 linear voltage regulator
provides a regulated power supply to the bus-side circuitry of
the ADM2481.
ISOLATION
VCC BARRIER
SD103C
TRANSFORMER
DRIVER
VCC
+
22µF
78253
SD103C
VCC
5V
IN OUT
SD ADP3330
+
10µF
ERR
NR GND
VDD1
VDD2
ADM2481
GND1
GND2
Figure 30. Isolated Power Supply Circuit
Rev. A | Page 16 of 20


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Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16 9
7.60 (0.2992)
7.40 (0.2913)
1 8 10.65 (0.4193)
10.00 (0.3937)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.33 (0.0130)
0.20 (0.0079)
0.75 (0.0295)
0.25 (0.0098) 45°
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADM2481BRWZ
ADM2481BRWZ-RL7
EVAL-ADM2481EBZ
1 Z = RoHS Compliant Part.
Data Rate (kbps)
500
500
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead, Wide Body SOIC_W
16-Lead, Wide Body SOIC_W
ADM2481 Evaluation Board
ADM2481
Package Option
RW-16
RW-16
Rev. A | Page 17 of 20


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NOTES
Data Sheet
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Data Sheet
NOTES
ADM2481
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ADM2481
NOTES
Data Sheet
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08920-0-6/12(A)
Rev. A | Page 20 of 20





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