DMA2280

 

C/D/D2-MAC Decoder

 

 

 

Micronas

Micronas



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MICRONAS
INTERMETALL
DMA 2271,
DMA 2280,
DMA 2281
C/D/D2–MAC Decoder
Edition August 5, 1991
6251–331–1E
MICRONAS


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DMA 2271, DMA 2280, DMA 2281
Contents
Page
Section
3 1.
3 1.1.
3 1.2.
5 2.
5 2.1.
5 2.2.
6 2.3.
8 2.4.
9 2.5.
9 2.5.1.
9 2.5.2.
11 2.5.3.
12 2.5.4.
15 2.5.5.
17 2.5.6.
20 2.5.7.
21 3.
21 3.1.
21 3.1.1.
21 3.1.2.
21 3.1.3.
21 3.1.4.
21 3.2.
21 3.2.1.
22 3.2.2.
22 3.2.3.
22 3.2.4.
22 3.2.5.
22 3.2.6.
22 3.2.7.
22 3.2.8.
22 3.3.
23 3.3.1.
23 3.3.2.
23 3.3.3.
23 3.3.4.
24 3.3.5.
24 3.3.6.
25 4.
25 4.1.
25 4.2.
25 4.2.1.
25 4.2.2.
25 4.3.
26 4.3.1.
Title
Introduction
General Information
Environment
Specifications
Outline Dimensions
Pin Connections
Pin Descriptions
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Crystal Characteristics
Characteristics
DRAM Interface Characteristics
Waveforms
Frequency Responses
Functional Description
Clock and Data Recovery
The Code Converter
The Video Clamping Circuit and the AGC Circuit
The Phase Comparator and the PLL Filter
The Data Slicer and the Synchronization Circuit
Video Processing
The Luminance Store
The Luminance Interpolating Filter
The Contrast Multiplier
The Chrominance Store
The Line Interpolating Filter
The Chrominance Interpolating filter
The Color Saturation Multiplier
The Color Multiplier
Sound/Data Processing
The Golay and PT Byte Decoder
The Address Comparator
The Sound Decoder
The Sound Multiplex
The ΦA Audio Clock
The Buffer for Packet 0
The Three Serial Interfaces
The S Bus Interface and the S Bus
The IM Bus Interface and the IM Bus
The IM Bus
IM Bus Addresses and Instructions
The Burst Bus
Control and Status Registers
2


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DMA 2271, DMA 2280, DMA 2281
The DMA 2271, DMA 2280, and DMA 2281 C/D/
D2–MAC Decoders
1. Introduction
1.1. General Information
Digital real–time signal processor for processing C/D/
D2–MAC video, sound, and data signals digitized by the
VCU 2133 Video Codec in digital CTV receivers accord-
ing to INTERMETALL's DIGIT 2000 system of or in ana-
log CTV receivers or in stand–alone C/D/D2–MAC de-
coders (see Figs. 1–1 to 1–3).
In order to receive TV channels transmitted via satellite
or cable network using the newly established C/D/
D2–MAC standards instead of PAL or SECAM, decod-
ers are required for decoding the TV video and sound
signals. The DMA 2271, DMA 2280, and DMA 2281 are
suitable for this purpose, in conjunction with the DIGIT
2000 digital TV system and also for stand–alone solu-
tions.
The DMA 2271 is only able to decode D2–MAC/packet
signals, in contrast to the DMA 2280 which decodes D–
MAC/packet signals and the DMA 2281 which decodes
D2, D or C–MAC/packet signals.
The DMA 2271, DMA 2280, and DMA 2281 are a pro-
grammable circuits, produced in CMOS technology and
housed in a 68–pin PLCC package. These decoders
contain on a single silicon chip the following functions
(see Fig. 1–4):
– code converter
– circuitry for clamping, AGC and PLL
– chroma and luma store for expansion of the MAC sig-
nal
– chroma and luma interpolating filter
– contrast multiplier with limiter for the luminance signal
– color saturation multiplier with multiplexer
– duobinary decoder (data slicer)
– synchronization
– descrambler and de–interleaver
– packet linker
– packet 0 buffer
– sound decoder and sound multiplexer
– IM bus interface circuit for communicating with the
CCU
1.2. Environment
Fig. 1–1 shows the block diagram of a digital CTV receiv-
er system DIGIT 2000, equipped with C/D/D2–MAC and
Teletext, and suited for the PAL and SECAM standards.
Stand–alone C/D/D2–MAC decoders are shown in Figs.
1–2 and 1–3. These two versions can either be inte-
grated into analog CTV receivers, or can serve as
stand–alone C/D/D2–MAC decoders.
CCU 3000
NVM 3060
DPU 2553
DRAM
TPU 2735
Defl.
Video 1/2
VCU 2136
SPU 2243
1/2
VCU 2136
R
G
B
PVPU 2204
MCU 2600
DMA 2281
AMU 2481
Sound
DRAM
ACP 2371
S1
S2
S3
S4
Fig. 1–1: Block diagram for a multistandard CTV re-
ceiver according to the DIGIT 2000 system and
equipped with D2–MAC
CCU 3000 DRAM
TPU 2735
Video VCU 2133
A/D Part
DMA 2281
VCU 2133
D/A Part
Defl.
R
G
B
DRAM
MCU 2600
AMU 2481
S1
S2
S3
S4
Fig. 1–2: Block diagram for a stand–alone C/D/
D2–MAC decoder, equipped with the VCU 2133 Video
Codec for A/D and D/A conversion (reduced chroma
bandwidth)
3


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DMA 2271, DMA 2280, DMA 2281
CCU 3000 DRAM
TPU 2735
Video 1/2
UVC 3130
DMA 2281
DRAM
HDAA
R
G
switch
B
R
G
B
MCU 2600
AMU 2481
S1
S2
S3
S4
Fig. 1–3: Block diagram for a stand–alone C/D/
D2–MAC decoder, equipped with the UVC 3130 for
A/D and HDAA or D/A conversion (full chroma band-
width)
39–46
DMA 2271, DMA 2280, DMA 2281
Gray
Converter
Luma
Store
Luma
Inter-
polating
Filter
31–38 18 21–24, 27–30
8 ODI 8
Contrast
Multiplier
Color
Multiplexer
48 Clamping
49 AGC
25 Phase
Com-
parator,
26 PLL Filter
Chroma
Store
Line
Inter-
polating
Filter
Chroma
Interpo-
lating
Filter
Color
Saturation
Multiplier
50–53
57
58
60
69
4
Data
Slicers,
Synchro-
nization
Des-
crambler,
Deinter-
leaver
Packet
Linker
Error
Correction,
Expansion,
Error
Concealment
8
Memory
Control
54 T0
12
IM–Bus
13 Interface
14
Golay,
PT byte
and TG
Decoder
Address
Com-
parator
ΦM RESET
VSUP
Buffer
for
Packet 0
Sound
Multiplex
Audio
Clock
Generator
2–6
9–1
1
8
68
7
1
64
66
67
65
62 15 61 63
55 56
16
Fig. 1–4: Block diagram of the DMA 2271, DMA 2280, DMA 2281 C/D/D2–MAC decoders
17
4


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DMA 2271, DMA 2280, DMA 2281
2. Specifications
2.1. Outline Dimensions
Fig. 2–1: DMA 2271, DMA 2280, DMA 2281 in 68–pin
PLCC package
Weight approx. 4.5 g,
Dimensions in mm
2.2. Pin Connections
Pin Nr. Signal Name
Symbol
1
RAM Data Input/Output
RDAT
2 RAM Address Output 0 (LSB) RA0
3 RAM Address Output 1 RA1
4 RAM Address Output 2 RA2
5 RAM Address Output 3 RA3
6 RAM Address Output 4 RA4
7
RAM Read/Write Output
R/WQ
8 Row Address Select Output RASQ
9 RAM Address Output 5 RA5
10 RAM Address Output 6
RA6
11 RAM Address Output 7 (MSB) RA7
12 IM Bus Clock Input
IMC
13 IM Bus Ident Input
IMI
14
IM Bus Data Input/Output
IMD
15 Reset Input
RESQ
16 18.432 MHz Output
XTAL1
17 18.432 MHz Input
XTAL2
18 Output Disable Input
ODI
19 leave vacant
20 leave vacant
21 Chroma Output 7 (MSB) CO7
22 Chroma Output 6
CO6
23 Chroma Output 5
CO5
24 Chroma Output 4
CO4
25 PLL Tuning Data Output PLLD
26
PLL Tuning Clock Output
PLLC
27 Chroma Output 3
CO3
28 Chroma Output 2
CO2
29 Chroma Output 1
CO1
30 Chroma Output 0 (LSB)
CO0
31 Luma Output 0
LO0
32 Luma Output 1
LO1
33 Luma Output 2
LO2
34 Luma Output 3
LO3
35 Luma Output 4
LO4
36 Luma Output 5
LO5
37 Luma Output 6
LO6
38 Luma Output 7 (MSB)
LO7
39
Baseband Input 7 (MSB)
BI7
40 Baseband Input 6
BI6
41 Baseband Input 5
BI5
42 Baseband Input 4
BI4
43 Baseband Input 3
BI3
44 Baseband Input 2
BI2
45 Baseband Input 1
BI1
46 Baseband Input 0 (LSB) BI0
47 leave vacant
48 Clamping Output
CLMP
49 AGC Output
AGC
50 Combined Output for Horizon- KEY
tal Blanking and Key
5


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DMA 2271, DMA 2280, DMA 2281
51 Combined Output for Horizon- CBL
tal and Vertical Blanking
52 Data Burst Window Output DBW
53 Composite Sync Output
CSYNC
54 Test Input/Output
T0
55 Packet Data Output
PDAT
56 Descrambled Packet Data In- DPDAT
put
57 Teletext Sync Output
TSYNC
58 Burst Sync Output
BSYNC
59 Burst Data Input/Output
BDAT
60 Burst Clock Output
BCLK
61 Ground
GND
62 Main Clock Input
MCLK
63 Supply Voltage
VSUP
64 Sound Bus Ident Output SBI
65 Audio Clock Output
ACLK
66 Sound Bus Data Output
SBD
67 Sound Bus Clock Output SBC
68 Column Address Select Out- CASQ
put
2.3. Pin Descriptions
Pin 1 – RAM Data Input/Output RDAT (Fig. 2–7)
serves as an output for writing data into the external
RAM and as an input for reading data from the external
RAM.
Pins 2 to 6 and 9 to 11 – RAM Address Outputs RA0 to
RA7 (Fig. 2–10)
These pins are used for addressing the external RAM.
Pin 7 – RAM Read/Write Output R/WQ (Fig. 2–10)
By means of this output the external RAM is switched to
read or write mode.
Pin 8 – Row Address Select Output RASQ (Fig. 2–10)
This pin supplies the Row Address Select signal to the
external RAM.
Pins 12 to 14 – IM Bus Connection IMC, IMI,IMD (Figs.
2–2 and 2–6)
These pins connect the DMA 2271, DMA 2280 and DMA
2281 to the IM bus. Via the IM bus the DMA 2271, DMA
2280 and DMA 2281 communicate with the CCU 3000
6
Central Control unit. The data transferred via the IM bus
are listed in tables 4–1 to 4–4.
Pin 15 – Reset Input RESQ (Fig. 2–5)
Pin 15 is used for hardware reset. Reset is actuated at
Low level, at High level the DMA 2271, DMA 2280, and
DMA 2281 are ready for operation.
Pins 16 and 17 – XTAL 1 Output and XTAL 2 Input (Fig.
2–11)
These oscillator pins are used to connect an 18.432
MHz crystal, which determines the ACLK audio clock
signal supplied by pin 65. Alternatively, an 18.432 MHz
clock may be fed to pin 17.
Pin 18 – Output Disable Input ODI
This input serves for fast switchover of the luma and
chroma outputs (L0 to L7 and C0 to C7) to high imped-
ance, which is required if the TV receiver is equipped
with Picture–in–picture. Low means outputs active, High
means outputs are disabled.
Pin 19 – leave vacant
Pin 20 – leave vacant
Pins 21 to 24 and 27 to 30 – Chroma Outputs C7 to C0
(Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280, and DMA
2281 deliver the digital chrominance signal (R–Y, B–Y)
in multiplexed operation to the VCU 2133 Video Codec
Unit, where it is converted to an analog signal.
Pin 25 – PLL Tuning Data Output PLLD (Fig. 2–8)
This pin supplies the 12–bit data word containing the
PLL tuning information from the PLL filter of the DMA
2271, DMA 2280, and DMA 2281. This information is
needed by the voltage controlled oscillator (VCO) con-
tained on the MCU 2600 Clock Generator IC and closes
the PLL which determines the main clock signal.
Pin 26 – PLL Tuning Clock Output PLLC (Fig. 2–8)
This pin supplies the data clock signal needed for the se-
rial data transfer of the 12–bit PLL tuning information.
Pins 31 to 38 – Luma Outputs L0 to L7 (Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280 and DMA
2281 deliver the digital luminance signal to the VCU
2133 Video Codec Unit, where it is converted to an ana-
log signal.
Pins 39 to 46 – Baseband Input BI7 to BI0 (Fig. 2–3)
Via these inputs, the DMA 2271, DMA 2280, and DMA
2281 receive the digitized baseband signal from the
VCU 2133 Video Codec.
Pin 47 – leave vacant
Pin 48 – Clamping Output CLMP (Fig. 2–9)
This pin supplies a PDM (Pulse Density Modulated) sig-
nal for clamping the analog baseband signal at the input
of the analog to digital converter.


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DMA 2271, DMA 2280, DMA 2281
Pin 49 – AGC Output AGC (Fig. 2–9)
This tristate–controlled output allows automatic gain
control (AGC) with a three–level signal. High level
means that the input level of the baseband signal is too
low, low level means that the input level of the baseband
signal is too high. In the high impedance state the level
of the baseband signal is in the proper range.
Pin 50 – Combined Output for Horizontal Blanking and
Color KEY (Fig. 2–9)
This output is a tristate–controlled output. In conjunction
with the input load represented by the VCU 2133 Video
codec, the three level blanking and key is produced.
High level means active line, high impedance state
means horizontal blank and low level means color key.
Pin 51 – Combined Output for Horizontal Blanking and
Vertical Blanking CBL (Fig. 2–9)
In conjunction with the input load represented by the
VCU 2133 Video Codec, the three level combined blank-
ing pulse is produced. High level means active line, high
impedance means horizontal blanking and low level
means vertical blanking.
Pin 52 – Data Burst Window DBW (Fig. 2–9)
This output supplies the data burst window signal which
can be used to switch an external de–emphasis net-
work. This signal is active high in line 625 and during the
data burst in each line.
Pin 53 – Composite Sync Output CSYNC (Fig. 2–8)
This output supplies a composite synchronization signal
as it may be used by the DPU 25xx Deflection Processor
or by other units which need a composite synchroniza-
tion signal which is not contained in the MAC baseband
signal.
Pin 54 – Test Input/Output T0 (Fig. 2–8)
This pin is used for testing the DMA 2271, DMA 2280,
and DMA 2281 during production.
Pin 55 – Packet Data Output PDAT (Fig. 2–10)
PDAT is used to put out each received packet, de–inter-
leaved, with Golay corrected header and with error–cor-
rected BT Byte. This pin used to connect the DMA 2275,
DMA 2285 or DMA 2286 Descrambler IC.
Pin 56 – Descrambled Packet Data Input DPDAT (Fig.
2–2)
This pin is used in conjunction with PDAT, if conditional
access signals must be descrambled, DPDAT receives
the descrambled packet data from the DMA 2275, DMA
2285 or DMA 2286 Descrambler IC.
Pin 57 – Teletext Sync Output TSYNC (Fig. 2–9)
This pin supplies a signal which marks the part of the VBI
lines containing Teletext data.
Pin 58 – Burst Sync Output BSYNC (Fig. 2–4)
This connection supplies a synchronization signal for
the Burst Data Output. The Sync Pulse marks the Line
Synchronization Word LWS of each, and the Clock Run
In CRI and Frame Sync Word FSW in line 625.
Pin 59 – Burst Data Output BDAT (Fig. 2–4)
This output supplies the recovered an decoded duobina-
ry data contained in a MAC signal. This signal may serve
as an input signal for the TPU 27xx Teletext Processor
or the DMA 2275, DMA 2285, DMA 2286 MAC Des-
crambler processor or for other purposes.
Pin 60 – Burst Clock Output BCLK (Fig. 2–9)
This pin supplies the data clock signal required for the
serial data transfer of the Burst Data signal. The fre-
quency of this signal is equal MCLK or MCLK/2 con-
trolled by parameter Data Rate Select DRS via IM Bus.
Pin 61 – Ground GND
Pin 62 – Main Clock Input MCLK (Fig. 2–4)
By means of this input, the DMA 2271, DMA 2280 and
DMA 2281 receive the required main clock signal from
the MCU 2600 Clock Generator IC.
Pin 63 – Supply VSUP
Pin 64, 66, and 67 – Sound Bus Ident SBI (Fig. 2–9)
Data SBD and Clock SBC (Fig. 2–8)
These pins supply the Clock, Data and Ident signals to
the AMU 2481 Mixing Unit via the serial three–line
Sound Bus.
Pin 65 – Audio Clock Output ACLK (Fig. NO TAG)
This pin supplies the ACLK Audio Clock signal for the
AMU 2481.
Pin 68 – Column Address Select CASQ (Fig. 2–10)
This pin supplies the Column Address Select signal for
the external RAM.
7


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DMA 2271, DMA 2280, DMA 2281
2.4. Pin Circuits
The following figures schematically show the circuitry at
the various pins. The integrated protection structures
are not shown. The letter “P” means P–channel, the let-
ter “N” N–channel.
VSUP
P
N
GND
Fig. 2–2:
Input Pins 12, 13, 18 and
56
VSUP
PP
NN
BIAS
GND
Fig. 2–3:
Input Pins 39 to 46
VSUP
P
N
N
GND
Fig. 2–6:
Input/Output Pin 14
VSUP
PP
NN
Fig. 2–7:
GND Input/Output Pin 1
VSUP
N
GND
Fig. 2–8:
Output Pins 21 to 38, 48,
52 to 54, 66 and 67
VSUP
P
N
P
N
GND
Fig. 2–4:
Input Pin 62
VSUP
P
N
GND
Fig. 2–9:
Output Pins 48 to 52, 57
to 60 and 64
VSUP
PN
P
N
NP
Fig. 2–5:
GND Input Pin 15
VSUP
P
N
GND
Fig. 2–10:
Output Pins 2 to 11, 55
and 68
8


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DMA 2271, DMA 2280, DMA 2281
16
0.5M
17
VSUP
P
P
N f ECLK
N
GND
Fig. 2–11:
Crystal Oscillator Pins 16 and 17
VSUP
N
P
GND
2.5. Electrical Characteristics
All voltages are referred to ground.
2.5.1. Absolute Maximum Ratings
Symbol
TA
TS
VSUP
VI
VO
IO
Parameter
Ambient Operating Temper-
ature
Storage Temperature
Supply Voltage
Input Voltage, all Inputs
Output Voltage, all Outputs
Output Current, all Outputs
Pin No.
19, 47, 63
Min.
0
–40
–0.3 V
–0.3 V
–10
Fig. 2–12:
Output Pin 65
Max.
65
+25
6
VSUP
VSUP
+10
Unit
°C
°C
V
mA
2.5.2. Recommended Operating Conditions at TA = 0 to 65 °C, fΦM = 20.25 MHz
Symbol
VSUP
VΦMIDC
VΦMIAC
tΦMIH
tΦMIL
tΦMIHL
VREIL
VREIH
tREIL
VVIL
VVIH
Parameter
Supply Voltage
ΦM Clock Input D.C. Voltage
ΦM Clock Input
A.C. Voltage (p–p)
ΦM Clock Input High/Low
Ratio
ΦM Clock Input High to Low
Transition Time
Reset Input Low Voltage
Reset Input High Voltage
Reset Input Low Time
Video Input Low Voltage
Video Input High Voltage
Pin No.
19, 47, 63
62
15
39 to 46
Min.
4.75
1.5
0.8
0.9
2.4
2
2.8
Typ.
5.0
1.0
Max.
5.25
3.5
2.5
1.1
0.15
fΦM
0.8
2.2
Unit
V
V
V
V
V
µs
V
V
9


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DMA 2271, DMA 2280, DMA 2281
Recommended Operating Conditions, continued
Symbol
VΦVIH
VVISΦ
VODIL
VODIH
VDSIL
VDSIH
VΦAL
VΦAH
Parameter
Video Input Hold Time after
ΦM Clock Input
Video Input Setup Time be-
fore ΦM Clock Input
Outputs Disable Inputs
Low Voltage
Outputs Disable Inputs
High Voltage
Descrambled Data Input
Low Voltage
Descrambled Data Input
High Voltage
ΦA Clock Input Low Voltage
ΦA Clock Input High Voltage
Pin No.
39 to 46,
62
18
56
17
tΦAH
tΦAL
tΦAHL
tΦALH
fΦA
VIMIL
VIMIH
fΦI
tIM1
tIM2
tIM3
tIM4
tIM5
tIM6
ΦA Clock Input
High/Low Ratio
ΦA Clock Input High to Low
Transition Time
ΦA Clock Input Low to High
Transition Time
ΦA Clock Input Frequency
IM Bus Input Low Voltage
IM Bus Input High Voltage
ΦI IM Bus Clock Frequency
ΦI Clock Input Delay Time
after IM Bus Ident Input
ΦI Clock Input
Low Pulse Time
ΦI Clock Input
High Pulse Time
ΦI Clock Input Setup Time
before Ident Input High
ΦI Clock Input Hold Time
after Ident Input High
ΦI Clock Input Setup Time
before Ident End–Pulse
Input
12 to 14
Min.
14
4
2.4
2.4
VSUP
–0.8V
0.9
2.4
0.05
0
3.0
3.0
0
1.5
6.0
Typ.
Max.
––
– 0.8
––
– 0.8
––
– 0.8
––
1.0 1.1
18.432
0.15
fΦA
0.15
fΦA
0.8
1000
––
––
––
––
––
Unit
ns
ns
V
V
V
V
V
MHz
V
V
kHz
µs
µs
µs
µs
10


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DMA 2271, DMA 2280, DMA 2281
Recommended Operating Conditions, continued
Symbol
tIM7
tIM8
tIM9
tIM10
Parameter
IM Bus Data Input Delay
Time after ΦI Clock Input
IM Bus Data Input Setup
Time before ΦI Clock Input
IM Bus Data Input Hold Time
after ΦI Clock Input
IM Bus Ident End–Pulse
Low Time
Pin No.
12 to 14
Min.
0
0
0
3.0
Typ. Max.
––
––
––
––
Unit
µs
2.5.3. Recommended Crystal Characteristics
Symbol Parameter
Min.
Typ.
Max.
Unit
TA Ambient Operating Temperature
–20
fp Parallel Resonance Frequency
fp Accuracy of Adjustment
fp
fp Frequency Deviation versus Temperature –
fp
Rr Series Resistance
C0 Shunt Capacitance
5.5
C1 Motional Capacitance
15
P Rated Drive Level
18.432*)
+85
±40
±40
– 50
– 7.5
– 20
0.02 –
°C
MHz
ppm
ppm
pF
fF
mW
fp Spurious Frequency Attenuation
20 –
dB
fH
*) at CL = 10 pF. This frequency applies for a certain application. For other applications, an appropriate frequency must
be chosen.
11


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DMA 2271, DMA 2280, DMA 2281
2.5.4. Characteristics at TA = 0 to 65 °C, VSUP = 4.75 to 5.25 V, fΦM = 20.25 MHz
Symbol
ISUP
VΦAOL
VΦAOH
tΦAHL
fΦA
VLCOL
ILCOH
tLCOT
tΦLCOH
tΦLCOS
tLD
VPOL
IPOH
fΦP
Parameter
Supply Current
ΦA Audio Clock Output
Low Voltage
ΦA Audio Clock Output
High Voltage
ΦA Audio Clock Output
High to Low Transition Time
ΦA Audio Clock Output
Frequency
Luma/Chroma Output
Low Voltage
Luma/Chroma Output
High Current
Luma/Chroma Output
Transition Time
Luma/Chroma Output Hold
Time after ΦM Clock Input
Luma/Chroma Output Setup
Time after ΦM Clock Input
Luma Output Delay Time after
PLL Bus Output Low Voltage
PLL Bus Output High Current
ΦP Clock Frequency
Pin No.
63
65
21 to 24,
27 to 38
21 to 24,
27 to 38,
62
25, 26
26
Min.
3.0
12
–194
tΦPOH
tΦPOL
tPDOSΦ
tΦPDOH
VSOL
ISOH
tSOT
fΦS
ΦP Clock Output
High/Low Ratio
PLL Data Output Setup
Time before ΦP Clock Output
PLL Data Output Hold
Time after ΦP Clock Output
S Bus Output Low Voltage
S Bus Output High Current
S Bus Output Transition Time
ΦS S Clock Output Frequency
25, 26
64, 66, 67
67
0.8
20
80
tS2 ΦS S Clock Output
tS1 High/Low Ratio
0.9
tS3
ΦS S Clock Output Setup Time 64, 67
160
before Ident End–Pulse Output
Typ.
100
Max.
130
2.0
––
– 10
18.432 –
– 0.3
– 10
– 10
––
– 30
– +839
– 0.2
– 10
fΦM
4
1 1.25
––
––
– 0.2
– 10
– 10
fΦA
4
1 1.1
220 –
Unit
mA
V
V
ns
MHz
V
µA
ns
ns
ns
µs
V
µA
ns
ns
V
µA
ns
ns
Test Conditions
IΦAO = 0.5 mA
–IΦAO = 0.5 m A
ILCO = 6 mA
VLCO = 5 V
IPO = 2 mA
VPO = 5 V
ISO = 2 mA
VSO = 5 V
12


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DMA 2271, DMA 2280, DMA 2281
Characteristics, continued
Symbol
tS4
tS5
tS6
VBOL
VBOH
tBT
fΦB
Parameter
Pin No.
S Bus Data Output Setup Time
before ΦS S Clock Output
66, 67
S Bus Data Output Hold Time
after ΦS S Clock Output
S Bus Ident End–Pulse
Output Low Time
64
Burst Bus Output Low Voltage 58 to 60
Burst Bus Output High Voltage
Burst Bus Output
Transition Time
ΦB Burst Bus Clock Frequency 60
tB3 ΦB Clock Output
tB2 High/Low Ratio
tB1
ΦB Clock Output Delay Time
58, 60
after Ident Output
tB4 Ident Output Delay Time after
ΦB Clock
tB5 Burst Bus Data Output Setup 59, 60
Time before ΦD Clock Output
tB6 Burst Bus Data Output Hold
Time after ΦB Clock Output
VIMOL
IIMOH
IM Bus Data Output Low Voltage 14
IM Bus Data Output
High Current
t4 IM Bus Data Output Setup Time 14, 12
before ΦI Clock Input High
t5 IM Bus Data Output Hold Time
after ΦI Clock Input Fall
VCLOL
VCLOH
VAGCOL
IAGCOZ
Clamping Output Low Voltage
Clamping Output High Voltage
AGC Output Low Voltage
AGC Output High–Impedance
Current
48
49
VAGCOH
tAGCO
tSAGCO
VHBCKOL
AGC Output High Voltage
AGC Output Pulse Duration
AGC Output Pulse Start Time
Combined Horizontal Blanking
& Color Key Output Low Voltage
50
IHBCKOZ
Combined Horizontal Blanking
and Color Key Output High–Im-
pedance Current
Min.
100
Typ.
Max.
Unit
ns
100 –
300 400 –
––
2.8 –
––
0.4
10
fΦM or
2 fΦM
0.9 1
1.1
ns
ns
V
V
ns
– 0– –
– 0– –
– 50 – ns
– 0– –
– – 0.3 V
– – 10 µA
0 –– –
0 –– –
––
––
––
–10 –
VSUP –0.5
40
– line No. 624
––
–10 –
0.2 V
VSUP –0.5
0.4
V
V
+10 µA
–V
– ms
––
0.4 V
+10 µA
Test Conditions
IDMO = 1.6 mA
–IDMO = 0.1 mA
IIMO = 6 mA
VIMO = 5 V
ICLO = 2 mA
–ICLO = 1 mA
IAGCO = 6 mA
VAGC = 0 to 5 V
–IAGC = 1 mA
IHBCKO = 6 mA
VHBCKO = 0 to 5 V
13


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DMA 2271, DMA 2280, DMA 2281
Characteristics, continued
Symbol
VHBCKOH
Parameter
Combined Horizontal Blanking &
Color Key Output High Voltage
Pin No.
50
Min.
4.0
tHB2 Horizontal Blanking Output Time
tCK2 Color Key High Z
Output Low Time
tCK1 Color Key Output Delay Time
after Horizontal Blanking Output
tHB1 Horizontal Blanking Output 50,
5.8
Lead Time before
21 to 24,
Chroma Output High
27 to 30
VHVBOL
Combined Horizontal and Verti- 51
cal Blanking Output Low Voltage
IHVBOZ
Combined Horizontal and
Vertical Blanking Output
High–Impedance Current
–10
VHVBOH
Combined Horizontal & Vertical
Blanking Output High Voltage
4.0
tVB1 Vertical Blanking Output Time
tHB2 Horizontal Blanking Output Time
VHBOL
Horizontal Blanking Output
Low Voltage
52
VHBOH
Horizontal Blanking Output
High Voltage
2.4
tHB2 Horizontal Blanking Output
Low Time
VCSOL
Composite Sync Output
53
Low Voltage
VCSOH
Composite Sync Output
High Voltage
2.8
tCS2 Composite Sync Output
Low Time 1
tCS3 Composite Sync Output
Low Time 2
tVB2
Composite Sync Output Delay
51, 53
Time after Vertical Blanking
Output
tCSOLC
Composite Sync Output Lead
Time before Chroma Output
53,
21 to 24,
27 to 30
4.2
VPDOL
VPDOH
Packet Data Output Low Voltage 55
Packet Data Output
High Voltage
2.4
VTSOL
Teletext Sync Output
Low Voltage
57 –
VTSOH
Teletext Sync Output
High Voltage
2.4
Typ.
10.5
2.27
5.5
0.64
10.5
12
4.8
2.4
1.5
Max.
Unit
V
0 µs
µs
µs
18.4 µs
0.4 V
+10 µA
–V
– ms
µs
0.4 V
–V
µs
0.4 V
–V
µs
µs
µs
16.8 µs
0.4 V
–V
0.4 V
–V
Test Conditions
–IHBCKO = 0.1 mA
IHVBO = 6 mA
VHVBO = 0 to 5 V
–IHVBO = 0.1 mA
IHBO = 1.6 mA
–IHBO = 0.1 mA
ICSO = 1.6 mA
–ICSO = 0.1 mA
IPDO = 1.6 mA
–IPDO = 0.1 mA
ITSO = 1.6 mA
–ITSO = 0.1 mA
14


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DMA 2271, DMA 2280, DMA 2281
2.5.5. DRAM Interface Characteristics
Symbol
VDIL
VDIH
tDIS
tDIH
VDOL
VDOH
tDT
tDHR
tDS
tDH
VAOL
VAOH
tAT
tRAH
tASR
tAR
tCAH
tASC
VRASOL
VRASOH
tRAST
tRAS
tRP
tRSH
VCASOL
VCASOH
tPC
Parameter
Pin No.
Min.
RAM Data Input Low Voltage
RAM Data High Voltage
1
2.0
RAM Data Input Setup Time
before CAS Output High
1, 68
RAM Data Input Hold Time
after CAS Output High
0
RAM Data Output Low Voltage 1
RAM Data Output High Voltage
2.4
RAM Data Op. Transition Time
3
RAM Data Hold Time after
RAS Low
1, 8, 68
140
RAM Data Setup Time before
CAS Low
20
RAM Data Output Hold Time
after CAS Output Low
1, 68
80
RAM Address Output
Low Voltage
2 to 6,
9 to 11
RAM Address Output
High Voltage
2.4
RAM Address Output
Transition Time
3
Row Address Output Hold Time 2 to 6, 9 to 22
after RAS Output Low
11, 8
Row Address Output Setup
Time before RAS Output Low
30
Column Address Output Hold
Time after RAS Output Low
2 to 6, 9 to 125
11, 68
Column Address Output Hold
Time after CAS Output
70
Column Address Output Setup
Time before CAS Output
10
RAS Output Low Voltage
8
RAS Output High Voltage
2.4
RAS Output Transition Time
3
RAS Low Pulsewidth
125
RAS Output Precharge Time
130
RAS Output Hold Time after
CAS Output Low
8, 68
110
CAS Output Low Voltage
68
CAS Output High Voltage
2.4
Page Mode Cycle Time
170
Typ.
Max.
0.8
75
Unit
V
V
ns
33 ns
0.4 V
–V
50 ns
– ns
– ns
– ns
0.4 V
–V
50 ns
– ns
– ns
– ns
– ns
– ns
0.4
50
3000
V
V
ns
ns
ns
ns
0.4 V
–V
– ns
Test Conditions
IDO = 1.6 mA
–IDO = 0.1 mA
IAO = 1.6 mA
–IAO = 0.1 mA
IRASO = 1.6 mA
–IRASO = 0.1 mA
ICASO = 1.6 mA
–ICASO = 0.1 mA
15


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DMA 2271, DMA 2280, DMA 2281
DRAM Interface Characteristics, continued
Symbol
tCAST
tCP
tCAS
tRCD
tCSH
tCRP
VWOL
VWOH
tWT
tCWL
tWCH
tRCH
tRRH
Parameter
CAS Output Transition Time
CAS Output Precharge Time
CAS Low Pulsewidth
CAS Output Delay Time after
RAS Output
CAS Output Hold Time after
RAS Output
CAS Output Precharge Time
before RAS Output
WRITE Output Low Voltage
WRITE Output High Voltage
WRITE Output Transition Time
WRITE Low before CAS High
WRITE Command Hold Time
after CAS Low
READ Command Hold Time
after CAS High
READ Command Hold Time
after RAS High
Pin No.
68
68, 8
7
7, 68
7, 8
Min.
3
70
95
45
170
150
2.4
3
180
80
50
20
Typ.
Max.
50
150
Unit
ns
ns
ns
ns
– ns
– ns
0.4 V
–V
50 ns
– ns
– ns
– ns
– ns
Test Conditions
IWO = 1.6 mA
–IWO = 0.1 mA
16


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DMA 2271, DMA 2280, DMA 2281
2.5.6. Waveforms
H
Ident
L
H
Clock
L
Data
H
L
1 2 3 4 5 6 7 8 9 10 11 12 13
LSB
A
Section A
Address
MSB LSB
B
Section B
Data
H
Ident
L
tIM1
H
Clock
L
tIM2
tIM7 tIM8
tIM3
tIM9
tIM4 tIM5
Data
H
L
Address LSB
Address MSB
16
or 24
MSB
C
Section C
tIM10
tIM6
Data MSB
Fig. 2–13: IM bus waveforms
S–Ident
S–Clock
S–Data
H
L
H
L
H
L
S–Ident
H
L
S–Clock
H
L
S–Data
H
L
64 Clock Cycles
16 Bit Sound 1 16 Bit Sound 2 16 Bit Sound 3 16 Bit Sound 4
A
Section A
B
Section B
tS6
tS1 tS2
tS3
tS4 tS5
LSB of Sound 1
MSB of Sound 4
Fig. 2–14: S bus waveforms
17


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DMA 2271, DMA 2280, DMA 2281
H
Sync
L
H
Clock
L
Data
H
L
Line 1–624
Line 625
644 645 646 647 648 1 2 3 4 5 6 7 8 9 10 11
A
Section A
B
99 100 101 102 103 104 105
C
Sections B and C
Sync
H
L
tB1
Clock
H
L
tB2
tB5
tB3
tB6
tB4
Data
H
L
Fig. 2–15: Burst bus waveforms
WE VOH
VOL
RAS
VOH
VOL
CAS
VOH
VOL
DRAM VOH
ADDR. VOL
DOUT VOH
VOL
DIN VOH
VOL
tCWL
tAR
tCSH
tRCD
tRAS
tPC
tCP tCAS
tWCH
tRSH
tRRH
tRP
tASR tRAH tASC
tCAH
ROW ADDR.
COLUMN ADDR. 0
tDS tDH
VALID DATA
tDHR
COLUMN ADDRESS 1
VALID DATA
COLUMN ADDRESS 14
VALID DATA
tRCH
tCRP
ROW ADDR.
VALID
tDIS
DATA
tDIH
VALID DATA
VALID DATA
Fig. 2–16: DRAM waveform
18


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DMA 2271, DMA 2280, DMA 2281
Composite Synchronization
Pin 53
Vertical Blanking
internal
Horizontal Blanking
Pin 52
Combined Horizontal
and Vertical Blanking
Pin 51
Fig. 2–18a
First Frame
tVB1
Composite Synchronization
Pin 53
Vertical Blanking
internal
Fig. 2–18b
Horizontal Blanking
Pin 52
Combined Horizontal
and Vertical Blanking
Pin 51
Fig. 2–17: Synchronization signals
Second Frame
tVB1
Composite Synchronization
Pin 53
a
Vertical Blanking
internal
Composite Synchronization
Pin 53
b
Vertical Blanking
internal
Fig. 2–18: Details of Fig. 2–17
32 µs
tC52
tC53
tVB2
64 µs
tC52
tC53
tVB2
19


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DMA 2271, DMA 2280, DMA 2281
Chroma out
Pins 21–24, 27–30
Luma out
Pins
31–38
Composite
Synchronization out
Pin 53
tC52
Horizontal Blank out
Pin 52
Color Key
internal
tCK1
Combined Horizontal
Blanking and Color Key
Pin 50
Fig. 2–19: Timing of video and sync signals
tC51
tHB1
tHB2
tCK2
tLD
2.5.7. Frequency Responses
5
0
–5
–10
dB –15
–20
I
II
III
IV
–25
–30
–35
–40
012345678
f (MHz)
Fig. 2–20: Luminance channel frequency response
5
0
–5
–10
dB –15
–20
–25
IV
III
II
I
VIII
VI
VII
V
–30 VI
–35
–40
01234
f (MHz)
Fig. 2–21: Chrominance channel frequency response
Table 2–1: Selection of the luma filter response
Table 2–2: Selection of the chroma filter response
LFI Curve No.
0I
1 II
2 III
3 IV
CFI Curve No.
0I
1 II
2 III
3 IV
4V
5 VI
6 VII
7 VIII
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DMA 2271, DMA 2280, DMA 2281
3. Functional Description
The DMA 2271, DMA 2280 and DMA 2281 process the
digitized D2–MAC video signal supplied by the VCU
2133 or by the UVC 3130 in the various circuit parts
shown in Fig. 1–4. The resulting digital luminance and
chrominance signals are then reconverted to analog sig-
nals in the VCU or HDAA. The resulting digital audio sig-
nals are processed in the AMU 2481 Audio Mixer which
provides filtering of the medium–quality channels and al-
lows mixing of the four sound channels. The AMU’s digi-
tal output signals are reconverted to analog in the ACP
2371 Audio Processor, which additionally carries out
functions like adjustment of volume, bass and treble,
loudness, etc. Remaining digital data as service and
channel information in packet 0 or line 625 can be han-
dled by software via the IM bus or by additional hardware
which uses the serial B–Data interface (B–Data, B–
Clock and B–Sync). Section 1.2. shows how the DMA
2271, DMA 2280 and DMA 2281 can be used together
with other circuits of INTERMETALLS’s DIGIT 2000 di-
gital TV system to realize a multistandard
NTSC/PAL/SECAM/C/D/D2–MAC color TV receiver.
To understand the signal processing in the DMA 2271,
DMA 2280, and DMA 2281 it may be useful to distin-
guish three different function blocks, namely:
– Clock and Data Recovery
– Video Processing
– Sound/Data Processing
3.1. Clock and Data Recovery
3.1.1. The Code Converter
This circuit converts the digitized C/D/D2–MAC base-
band signal, delivered by the VCU 2133 in a parallel
Gray code, into a simple binary–coded signal. The func-
tion of the circuit is controlled by the CCU 3000 via the
IM bus (see section 4.2.).
3.1.2. The Video Clamping Circuit and the AGC Cir-
cuit
The video clamping circuit measures the DC voltage lev-
el of the clamp period and, by means of the pulse density
modulated signal from pin 48, sets the DC level of the
clamp period to a constant 5.5 V. The white and the black
levels in line 624 are measured for automatic gain con-
trol (AGC pin 49) and the two values are fed to the IM
bus interface which organizes the data communication
with the CCU.
AGC (pin 49) = high if WL – BL < 224
AGC (pin 49) = high impedance if 224 WL – BL 240
AGC (pin 49) = low if WL – BL > 240
3.1.3. The Phase Comparator and the PLL Filter
The phase comparator derives the reference signal from
the slopes contained in the data burst of each line. Its
output signal, an 8–bit word which is passed through a
digital lowpass filter, is added to an 8–bit word, VCOA,
which is provided by the CCU for adjustment of the crys-
tal frequency. This digital PLL signal is output via pins 25
and 26 and routed to the MCU 2600 Clock Generator IC
thus closing the PLL, existing between DMA 2271, DMA
2280, and DMA 2281, VCU 2133 Video Codec and MCU
2600 Clock Generator IC. In this way, the main clock sig-
nal FM of the system is in phase with the duobinary–
coded signal.
To adjust the crystal frequency, it is possible to render in-
operative the PLL by setting PLLO bit 4 in address 201
(Table 4–1). The VCO in the MCU is then free–running
and the center frequency can be aligned by varying the
data word VCOA (bits 0 to 7) in the IM bus address 14.
3.1.4. The Data Slicer and the Synchronization Cir-
cuit
The digitized C/D/D2–MAC baseband signal is filtered
by a 5 MHz lowpass filter before being routed to the data
slicer. The output of the slicer is connected to pin 59 (B–
Data). In phase with the continuous bit stream of 20.25
or 10.125 MBit/s, a clock signal (B–Clock), a synchroni-
zation signal (B–Sync) and a signal for Teletext informa-
tion (TTSYNC) are available at pins 60, 58, and 57 (see
Fig. 2–15).
The vertical synchronization pulse, on–chip, is derived
from a 64–bit correlator which compares the data stream
at the output of the slicer with the fixed Frame Synchroni-
zation Word (FSW). Whenever the correlation is equal
to or greater than 61 a frame reset pulse is generated.
Horizontal synchronization is derived by counting. In
phase with the video outputs (L0 to L7, C0 to C7), the
various synchronization and blanking signals are out-
puts at pins 50 to 53 (Fig. 2–17, 2–18 and 2–18).
3.2. Video Processing
The DMA 2271, DMA 2280, and DMA 2281 process the
C/D/D2–MAC baseband signal, digitized by the VCU or
UVC at a sample frequency of 20.25 MHz. For time ex-
pansion, the video samples of each line are stored in an
on–chip RAM and read to at the lower frequencies of
13.5 MHz for the luminance signal and 6.75 MHz for the
color difference signals.
3.2.1. The Luminance Store
Time expansion of the luminance signal is achieved by
digitizing the analog signal at a clock frequency of 20.25
MHz, storing the Bytes, and reading them at a frequency
of 13.5 MHz. For this, a fast RAM is provided on–chip.
21


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DMA 2271, DMA 2280, DMA 2281
3.2.2. The Luminance Interpolating Filter
An interpolation from 13.5 MHz to 20.25 MHz is per-
formed in order to overcome the need for a second sys-
tem clock of 13.5 MHz and to simplify the reconstruction
filters placed after the D/A conversion (RGB outputs of
the VCU). The interpolation filter has a linear phase and
can be switched to broad or narrow bandwidth by means
of the CCU via the IM bus (bits 10 and 11, address 201).
The different frequency responses are shown in Fig.
2–20 and in Table 2–1.
3.2.3. The Contrast Multiplier
After the luminance interpolating filter is a contrast multi-
plier. The contrast setting is controlled by the CCU via
the IM bus (bits 10 to 15, address 200), depending on the
user’s instruction. From the contrast multiplier, the digi-
tal luminance signal is fed back to the VCU 2133 in the
form of an 8–bit signal. In the VCU, this signal is con-
verted from digital to analog and fed to the RGB matrix.
The setting range of the contrast multiplier comprises 6
bits (64 steps). If the product at the multiplier’s output is
higher than the working range, the largest possible num-
ber is output.
3.2.4. The Chrominance Store
The chrominance store contains the color information
for 3 lines. It is used for time expansion and line interpo-
lation. The input frequency is 20.25 MHz, the output fre-
quency 6.75 MHz.
3.2.5. The Line Interpolating Filter
The color difference signals are transmitted within alter-
nate lines as U and V. A “1, 2, 1” post–filter required to
interpolate the color difference information is implem-
ented. The action of the filter is for even lines:
U = Un, V = Vn–1 + Vn +1
2
and for odd lines:
U = Un–1 + Un +1 , V = Vn
2
3.2.6. The Chrominance Interpolating Filter
After the line interpolating filter the 8–bit color difference
signals U and V are routed to the chroma interpolating
filter which has linear phase and can be switched to dif-
ferent frequency responses via the IM bus (Fig.
NO TAG, Table 2–2) using bits 13 to 15 in address 201.
This filter is used for conversion of the sample rate from
6.75 MHz up to 10.125 MHz.
3.2.7. The Color Saturation Multiplier
The digital color difference signals U and V are routed to
a color saturation multiplier, whose setting is also con-
trolled by the CCU via the IM bus (address 23). The
range of the multiplier comprises 6 bits, with each color
difference signal being set independently.
The PAL matrix in the VCU requires a compensation fac-
tor of 0.71. This means that the color saturation factor for
(B – Y) is equal to 0.71 the color saturation factor for
(R – Y). Both factors are calculated in the CCU.
3.2.8. The Color Multiplexer
The color difference signals are transferred back to the
VCU 2133 in multiplex via a 4–line bus. Demultiplexing
takes place in the VCU. The digital signals are then re-
converted to analog. Subsequently they are dematrixed
in the RGB matrix together with the Y signal, giving the
RGB signals which drive the output amplifiers of the
VCU 2133 Video Codec.
The color multiplexer can drive a 4–line bus with an ef-
fective sample rate of 5.6025 MHz for each color differ-
ence signal or an 8–line bus with a sample rate of 10.125
MHz. This function is controlled by the IM bus (Table
4–1), using bit 6 in address 201.
3.3. Sound/Data Processing
This section begins with a descrambler and de–inter-
leaver. The descrambler uses the same pseudo–ran-
dom binary sequence (PRBS) generator as is used for
the scrambling process. Its clock rate is 10.125 MHz or
20.25 MHz. The de–interleaver corrects the succession
of the transmitted packet bits which are interleaved in or-
der to minimize the effect of multiple bit errors.
Table 3–1: Transmission Order
1 95 189 283 377 471 565 659
2 96 190 284 378 472 566 660
... ...
... ...
... ...
93 187 281 375 469 563 657 751
94 188 282 376 470 564 658 (1)
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DMA 2271, DMA 2280, DMA 2281
3.3.1. The Golay and PT Byte Decoder
The data format has changed now from data burst for-
mat (99 bits) to packet format (751 bits). The header of
each packet contains defined addresses for the different
sound and data services and four bits representing the
sound characteristics. The PT Byte of each packet dis-
tinguishes between sound and data packets. After cor-
rection of header and PT Byte with the Golay and PT
Byte decoder, this information is used for automatic con-
figuration of the DMA 2271, DMA 2280, and DMA 2281.
In addition, the Golay decoder is used for measuring the
bit error rate of the transmission channel. The bits in er-
ror in each packet header are accumulated over one
frame (82 packets). The sum is stored in IM bus register
206 (Table 4–2) and can be read by the CCU which may
control different muting functions.
3.3.2. The Address Comparator
The DMA 2271, DMA 2280, and DMA 2281 D2–MAC
Decoders are able to treat different sound services auto-
matically by decoding the address field of the packet
header. The two continuity bits CI1 and CI0 are used to
link successive packets of the same service in case of
a 120 Byte sound coding service.
Among the different coding characteristics all combina-
tions are possible. The user can select up to four sound
channels simultaneously by programming the sound
services via the IM bus (address 203, 194, 195 and 196).
These addresses are compared with the address of
each transmitted sound packet. At correspondence, this
packet is selected and decoded.
3.3.3. The Sound Decoder
The sound decoding section converts all types of se-
lected sound packets into a sequence of 14–bit sound
samples. The medium–quality channels are up–
sampled to the 32 kHz sampling frequency of the high–
quality channels, i.e. every sample of a medium–quality
channel is put out twice, the second time as a zero sam-
ple. The second part of the interpolation is performed in
the AMU 2481 Audio Mixer where two oversampling fil-
ters are provided. The error correction section uses a
range check and/or Hamming decoder, depending on
the sound coding mode. The Hamming decoder is able
to correct one error per sample and to detect double er-
rors. The range check uses the highly protected scale
factor bits to check the MSBs of each sample. Its error
correction and detection abilities are shown in Table
3–2.
Erroneous samples, i.e. samples with uncorrectable er-
rors, are concealed by replacement with interpolated ad-
jacent samples. The storage capacity for buffering the
sound samples during processing and for obtaining a
smooth, regular output of sound samples is provided by
an external 64–K DRAM. To ensure the continuity of out-
put sound samples in case of packet loss or packet gain,
the silence information is used and blocks of samples
corresponding to “silence” are repeated or omitted.
3.3.4. The Sound Multiplex
After extension from 14 bits to 16 bits, the sound sam-
ples of the four channels are loaded into a 64–bit shift
register and transferred to the AMU 2481 Audio Mixer
via a serial 3–lines S bus. Fig. 2–14 shows the S bus tim-
ing.
Table 3–2: Error correction and detection
Scale Protec-
Factor tion
Range
linear:
111 1
110 2
101 3
011 4
100 5
010 6
001 7
000 8
companded:
010 6
001 7
000 7
Defective
Bits
Error Error
Correc- Detec-
tion tion
––
X13, X12
X13, X12, X11 –
X13 X10 1
X13 X9
1
X13 X8
2
X13 X7
2
X13 X6
2
1
2
2
3
3
4
4
X9, X8
X9, X8, X7
X9, X8, X7
1
2
2
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DMA 2271, DMA 2280, DMA 2281
3.3.5. The ΦA Audio Clock
The audio clock ΦA for the AMU 2481 Audio Mixer and
the ACP 2371 Audio Processor is also supplied by the
DMA 2271, DMA 2280 and DMA 2281 which generate
this 18.432 MHz clock by means of the crystal con-
nected to pins 16 and 17 and supply it via pin 65. The fre-
quency of 18.432 MHz is an integer multiple of the sound
sampling frequency (32 kHz).
The ΦA audio clock output pin 65 can be switched over
to the normal main clock ΦM if a standard other than C/
D/D2–MAC is received. For this, bit ACS in address 204
of the IM bus is provided (Table 4–1).
The clock frequency ΦS for the serial S bus is also
derived from the audio clock ΦA (pin 65) by dividing by
eight (18.432 MHz: 4 = 4.608 MHz)
3.3.6. The Buffer for Packet 0
One packet address (000H) is reserved for service and
network identification data. A 720–bit (90 Byte) Buffer is
implemented on–chip especially for this, and is con-
trolled by the CCU via the IM bus (bits 8 and 9, address
204). The following conditions must be met to ensure
that a received packet is stored in this buffer:
Packet Address
Packet Type
Data Group Type
Packet 0 Status
PA = 000H
PT = F8H
TG = selected type in IM bus
register 204
P0 = 0 (see IM bus registers 204
and 206)
The packet 0 buffer can be read sequentially from a
16–bit IM bus register (address 210, Table 4–2). One
complete read cycle takes about 1.5 ms (IM bus fre-
quency = 1 MHz). It is possible to reset and to clear the
buffer via the IM bus in order to repeat the last–read
cycle or to receive the next zero packet. Additionally, the
last 16 bits of the zero packet are used for error check-
ing. This CRC check calculates the 16–bit syndrom vec-
tor of the packet concerned and stores it in an IM bus
register. It can then be used by software for error detec-
tion.
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DMA 2271, DMA 2280, DMA 2281
4. The Three Serial Interfaces
4.1. The S Bus Interface and the S Bus
The S bus has been designed to connect the digital
sound output of the DMA 2271, DMA 2280, and DMA
2281 MAC Decoders or the MSP 2400 NICAM Demodu-
lator/Decoder to audio–processing ICs such as the AMU
2481 Audio Mixer or the ACP 2371 Audio Processor
etc., and to connect these ICs one to the other. The S bus
is a unidirectional, digital bus which transmits the sound
information in one direction only, so that it is not neces-
sary to solve priority problems on the bus.
The S bus consists of the three lines: S–Clock, S–Ident,
and S–Data. The DMA 2271, DMA 2280, and DMA 2281
or the MSP 2400 generates the signals S–Clock and S–
Ident, which control the data transfer to and between the
various processors which follow the DMA 2271, DMA
2280, and DMA 2281 or the MSP 2400. For this, the S–
Clock and S–Ident inputs of all processors in the system
are connected to the S–Clock and S–Ident outputs of the
DMA 2271, DMA 2280, and DMA 2281 or the MSP 2400.
S–Data output of the DMA 2271, DMA 2280, and DMA
2281 or MSP 2400 is connected to the S–Data input of
the next following AMU, the AMU’s S–Data output is
connected to the ACP’s S–Data input and so on.
The sound information is transmitted in frames of 64 bits,
divided into four successive 16–bit samples. Each sam-
ple represents one sound channel. The timing of a com-
plete transmission of four samples is shown in Fig. 2–14,
the times are specified under “Recommended Operat-
ing Conditions”. The transmission starts with the LSB of
the first sample. The S–Clock signal is used to write the
data into the receiver’s input register. the S–Ident signal
marks the end of one frame of 64 bits and is used as latch
pulse for the input register. The repetition rate of S–Ident
pulses is identical to the sampling rate of the D2–MAC
or NICAM sound signal; thus it is possible to transfer four
sound channels simultaneously.
The S bus interface of the DMA 2271, DMA 2280, and
DMA 2281 mainly consists of an output register, 64–bit
wide. The timing to write bit by bit is supplied by the S–
Clock signal. In the case of an S–Ident pulse, the con-
tents of the output register are written to the S–Data out-
put.
4.2. The IM Bus Interface and the IM Bus
4.2.1. The IM Bus
The INTERMETALL Bus (IM Bus for short) was de-
signed to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means the CCU acts
as a master, whereas all controlled ICs have purely
slave status.
The IM bus consists of three lines for the signals Ident
(ID), Clock (CL) and Data (D). The clock frequency
range is 50 Hz to 1 MHz. Ident and clock are unidirec-
tional from the CCU to the slave ICs, Data is bidirection-
al. bidirectionality is achieved by using open–drain out-
puts. The 2.5 ... 1 kOhm pull–up resistor common to all
outputs must be connected externally.
The timing of a complete IM Bus transaction is shown in
Fig. 5–2. In the non–operative state the signals of all
three bus lines are High. To start a transaction the CCU
sets the ID signal to Low level, indicating an address
transmission, and sets the CL signal to Low level, as well
as to switch the first bit on the Data line. Then eight ad-
dress bits are transmitted, beginning with the LSB. Data
takeover in the slave ICs occurs at the positive edge of
the clock signal. At the end of the address byte the ID sig-
nal switches to High, initiating the address comparison
in the slave circuits. In the addressed slave, the IM bus
interface switches over to Data read or write, because
these functions are correlated to the address. Also con-
trolled by the address the CCU now transmits eight or
sixteen clock pulses, and accordingly one or two bytes
of data are written into the addressed IC or read out from
it, beginning with the LSB.
The completion of the bus transaction is signalled by a
short Low state pulse of the ID signal. This initiates the
storing of the transferred data.
For future software compatibility, the CCU must write a
zero into all bits not used at present. Reading undefined
or unused bits, the CCU must adopt “don’t” care behav-
ior.
4.2.2. IM Bus Addresses and Instructions
By means of the IM bus, the DMA 2271, DMA 2280, and
DMA 2281 communicate with the CCU 3000 Central
Control Unit. The DMA 2271, DMA 2280, and DMA 2281
receive the instructions for the user–actuated settings
such as color saturation, contrast, sound channel select,
packet 0 control, etc., and transmits the measured or re-
ceived values such as bit error rate, signal level, sound
coding mode,packet 0 data, etc. The address numbers
and the associated data for this interaction via the IM bus
are shown in Tables 4–1 to 4–4. In these tables “W”
means data written by the CCU into the DMA, and “R”
means data read by the CCU from the DMA.
4.3. The Burst Bus
The Burst bus serves for transfer of the digitized
D2–MAC baseband signal, after code conversion, low-
pass filtering and slicing as described in sections 3.1.1.
and 3.1.4., to e.g., the TPU 2735 Teletext Processor or
the DMA 2275/DMA 2285/DMA 2286 MAC Descram-
bler. Timing of the B bus is shown in Fig. 2–15 and under
Recommended Operating Conditions.
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DMA 2271, DMA 2280, DMA 2281
4.3.1. Control and Status Registers
Note: Not–used bits must be set to zero for control (receive) registers and are don’t care for status (transmit) registers.
Table 4–1: 16–bit DMA control registers, instructions from CCU to DMA
Address Label
14 VCOA
14 VCOS
14 DI1
DI2
DI3
23 SAV
23 SAU
200 LD
200 CTS
200 CT
201 DSY
201 DCL
201 DLC
201 NIN
201 PLLO
201 STA
201 CMP
Bit No.
0–7
8–10
11
14
15
2–7
10–15
3–7
8
10–15
0
1
2
3
4
5
6
Default
Setting
0
Typical
Value
0
44
00
32 25
32 18
46
01
32 16
10
00
00
00
00
00
00
Function
VCO adjustment (range –128...+127)
alignment of the 20.25 MHz VCO
VCO select
1 = VCO3 selected
2 = VCO2 selected
4 = VCO1 selected
disable PLL output (pin 25, 26)
if (DI1 . or . DI2 . or DI3) then
PLL output = high impedance
saturation V adjust
0: gain = 0
63: gain = 2
saturation U adjust
0: gain = 0
63: gain = 2
luma delay adjust (range 0...30)
resolution: 20.25 MHz clock
luma contrast switch
luma contrast adjust
0: gain = 0
63: gain = 1 if CTS = 1
63: gain = 2 if CTS = 0
disable sync outputs (pins 50–53, 58–60)
0 = enabled
1 = high impedance
disable clamping output (pin 48)
0 = enabled
1 = high impedance
disable luma/chroma output (pin 21–24, 27–38)
0 = enabled
1 = high impedance
non interlace
0 = interlace on
1 = interlace off
PLL open
0 = PLL closed
1 = PLL opened
stand alone operation
0 = digital insertion
1 = stand alone
chroma output multiplex
0 = 4 x 4 multiplex
1 = 2 x 8 multiplex
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DMA 2271, DMA 2280, DMA 2281
Table 4–1, continued
Address Label
201 DGC
201 L525
201 LF
201 CF
202 BD
202 SD
203 C1A
203 C1E
203 C1U
203 C1M
194
195
196
197 SFS
197 CD
197 AUM
197 DRS
198 EDC
198 CLG
198 CS
Bit No.
7
Default
Setting
0
80
10–11
13–15
1–7
9–15
0
0
64
64
0–9
10
11
12–15
0
0
0
0
see register 203
see register 203
see register 203
0–10
7
13 0
14 0
15 0
0–3
4–5
14–15
0
0
0
Typical
Value
0
0
0
0
64
64
128
1
0
12
7
0
0
1
0
2
0
Function
disable gray code converter input signal (pin 39–45)
0 = gray coded
1 = binary coded
525 lines standard select
0 = 625 lines standard selected
1 = 252 lines standard selected
luma filter selection
chroma filter selection
horizontal blank delay adjust (pin 50–52)
resolution: 10.125 MHz clock
comp. sync delay adjust (pin 53)
resolution: 10.125 MHz clock
channel 1 packet address
channel 1 enable
channel 1 mode update
channel 1 mode
linear/nicam
hamming/parity protection
high/medium quality
stereo/mono
channel 2
channel 3
channel 4
subframe select
SFS = sample number of the first bit
in the selected subframe
examples:
DRS = 1, first subframe
SFS = 7
DRS = 1, second subframe SFS = 106
DRS = 0, first subframe
SFS = 14
chip definition
0 = DMA 2280
1 = DMA 2285
auto mode
0 = auto mode off
1 = sound coding in packet header
data rate select
0 = 10.125 Mbits/s
1 = 20.25 Mbits/s
D2–MAC
C/D–MAC
energy dispersal compensation (–8...+7)
clamping loop gain
chip select
0 = IM bus of DMA 2280 active
1 = IM bus of DMA 2285 active
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DMA 2271, DMA 2280, DMA 2281
Table 4–1, continued
Address Label
199 PLLS
199 ENF2
199 SLS
199 PLLG
199 FCD
199 BPH
199 SLL
204 SBE
204 DGT
204 POR
204 POC
204 DSB
204 ACS
204 ACF
Bit No.
0
1
2–3
4–5
6
7
8–15
0–3
4–7
8
9
10
11
12
Default
Setting
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Typical
Value
0
0
1
2
0
0
40
0
15
0
0
0
0
1
0
Function
PLL select
0 = D/D2 MAC PLL
1 = CMAC PLL
enable filter 2
0 for C/D MAC
1 for D2 MAC
slicer select
0 for D2–MAC
1 for D–MAC
2 for C–MAC
PLL gain
0 = maximal gain
3 = minimal gain
full channel data
0: DBW is gated (pin 52)
1: DBW is active all the time
burst phase
0 = with DMA 2285
1 = only DMA 2280
slice level (range –128...+127)
for D/D2–MAC
for C–MAC
S bus enable
channel 1 enable
channel 2 enable
channel 3 enable
channel 4 enable
data group type selection
packet 0 reset
1: select first byte in packet 0 buffer
(first byte = data group type DGT)
packet 0 clear
1: enable packet 0 buffer to store
next packet 0
disable S bus outputs (pins 64, 66, 67)
0 = enabled
1 = high impedance
audio clock switch (pin 65)
0: audio clock = main clock
1: audio clock = 18.432 MHz
audio clock free running
0 = audio clock locked to main clock
1 = audio clock free running
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DMA 2271, DMA 2280, DMA 2281
Table 4–1, continued
Address Label
205 T0
205 T1
205 T2
205 T3
205 T4
205 T5
205 T6
205 T7
205 T8
205 T9
205 T10
205 T11
205 T12
205 T13
205 T14
205 T15
Bit No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Default
Setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Typical
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
for test only
for test only
for test only
for test only
for test only
for test only
enable PDAT input
for test only
disable error concealment
for test only
enable BDAT input
for test only
for test only
disable luma/chroma interpolation filters
for test only
for test only
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DMA 2271, DMA 2280, DMA 2281
Table 4–2: 16–bit DMA status registers, information from DMA to CCU
Address
206
Label
BER
206 VER
206 C1S
206 C2S
206 C3S
206 C4S
206 P0S
206 SYNC
207 WL
207 BL
208 C1L
208 C2L
208 C3L
208 C4L
209 PSL
209 PSH
210 PDL
210 PDH
Bit No.
0–7
8–9
10
11
12
13
14
15
0–7
8–15
0–3
4–7
8–11
12–15
0–7
8–15
0–7
8–15
Function
bit error rate
number of erroneous bits detected by the golay decoder within the 82 packet
headers of one frame
version
0: C/D/D2–MAC Decoder
1: D2–MAC Decoder
2: D–MAC Decoder
3: C/D2–MAC Decoder
status of sound signal selected by C1A
0: sound signal is inactive or interrupted
1: sound signal is present
status of sound signal selected by C2A
0: sound signal is inactive or interrupted
1: sound signal is present
status of sound signal selected by C3A
0: sound signal is inactive or interrupted
1: sound signal is present
status of sound signal selected by C4A
0: sound signal is inactive or interrupted
1: sound signal is present
status of packet 0 buffer
0: packet 0 selected by DGT not received
1: packet 0 received
status of frame sync word detector
0: frame sync word not detected within 8 frames
1: frame sync word detected
white level measured in line 624 (typical value = 240)
black level measured in line 624 (typical value = 16)
coding law of sound signal selected by C1A
coding law of sound signal selected by C2A
coding law of sound signal selected by C3A
coding law of sound signal selected by C4A
L = 0: companded law
1: linear law
H = 0: first level protection
1: second level protection
HQ = 0: medium quality sound
1: high quality sound
S = 0: monophonic sound
1: stereophonic sound
packet 0 syndrom low byte
packet 0 syndrom high byte
PSL + PSH = 0: packet 0 received without error
PSL + PSH > 0: packet 0 received with error
packet 0 data low byte
packet 0 data high byte
30





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