gm6015

 

Digital TV Controller

 

 

 

Genesis

Genesis



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Genesis Microchip Publication
Preliminary Data Sheet
gm6015
Publication number: C6015-DAT-01B
Publication date: August 2002
Genesis Microchip Inc.
2150 Gold Street, P.O. Box 2150, Alviso, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365
165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422
George Thangiah Complex(E), 2nd Flr, 80 Feet Road, Jeevan Bhima Nagar, Bangalore 560 075, India, Tel 91-80-526 3878 Fax 91-80-529 6245
4F, No. 57, Sing Jung Road, NeiHu Taipei, Taiwan 114, R.O.C Tel: 886-2-2791-0118 Fax: 886-2-2791-0196
143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel 82-2-553-5693 Fax 82-2-552-4942
Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel (0755)386-0101, Fax (0755)386-7874
2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759
www.genesis-microchip.com / info@genesis-microchip.com


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Document History:
Revision
C6015-DAT-01A
C6015-DAT-01B
Initial Release
Editorial
Description
gm6015 Preliminary Data Sheet
Date
March 2002
August 2002
Related Documents:
Doc Number
C6010-DSR-01
Title
gm6010 / 6015 Programming Guide
Date
The following are Registered trademarks of Genesis Microchip Inc.:
GenesisTM
SageTM
FaroudjaTM
Genesis Display PerfectionTM
Ultra-Reliable DVITM
SmartsetTM
Intelligent Picture Processing™
DCDiTM
ESMTM
Real RecoveryTM
Jag-ASMTM
Adaptive Contrast Control™
TrueLifeTM
RealColorTM
SureSyncTM
Adaptive Backlight Control™
IntelliCombTM
© Copyright 2002
Genesis Microchip Inc.
All Rights Reserved.
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without
notice. It is the customer’s responsibility to obtain the most recent revision of the document. Genesis
Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or
omissions that may appear in this document.
August 2002
C6015-DAT-01B


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gm6015 Preliminary Data Sheet
Table of Contents
1. OVERVIEW............................................................................................................................ 1
1.1 Applications .................................................................................................................... 1
1.2 System Design Example ................................................................................................. 1
1.3 gm6015 Features............................................................................................................. 2
2. PINOUT DIAGRAM .............................................................................................................. 4
3. PIN DESCRIPTION ............................................................................................................... 5
4. FUNCTIONAL DESCRIPTION .......................................................................................... 11
4.1 Reset ............................................................................................................................. 12
4.1.1 Hardware Reset......................................................................................................... 12
4.1.2 Software Reset .......................................................................................................... 12
4.2 Bootstrap Configuration ............................................................................................... 12
4.3 Clock Generation and Distribution ............................................................................... 13
4.3.1 External Crystal / Oscillator ..................................................................................... 13
4.3.2 PLL / DDS ................................................................................................................ 13
4.3.3 Clock Domains ......................................................................................................... 15
4.4 Input Interface............................................................................................................... 16
4.4.1 Input Port Selection .................................................................................................. 16
4.4.2 Input Signals ............................................................................................................. 17
4.4.3 Input Video Formats ................................................................................................. 20
4.4.4 Input Sync Processing............................................................................................... 21
4.4.5 Input Capture Window.............................................................................................. 23
4.4.6 Input Format Measurement....................................................................................... 24
4.4.7 Wide Screen Signal (WSS) decoding ....................................................................... 25
4.5 Output Interface ............................................................................................................ 25
4.5.1 Output Signals .......................................................................................................... 25
4.5.2 656 Encoder .............................................................................................................. 27
4.5.3 VBI Data Insertion.................................................................................................... 28
4.5.4 Output Video Formats .............................................................................................. 28
4.5.5 Video Look Up Table ............................................................................................... 28
4.5.6 Dithering ................................................................................................................... 30
4.5.7 Output Configuration................................................................................................ 30
4.6 Color Space Conversion (CSC) .................................................................................... 34
August 2002
iii C6015-DAT-01B


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gm6015 Preliminary Data Sheet
4.6.1 Input CSC ................................................................................................................. 34
4.6.2 Output CSC............................................................................................................... 34
4.6.3 Color Control ............................................................................................................ 34
4.7 Video Processing .......................................................................................................... 35
4.7.1 MAIN Channel ......................................................................................................... 35
4.7.2 PIP Channel ............................................................................................................. 39
4.7.3 Video Processing Bypass.......................................................................................... 39
4.8 Synchronization Modes ................................................................................................ 40
4.9 Frame Store Interface.................................................................................................... 40
4.10 Interrupt ........................................................................................................................ 41
4.11 GPIO Pins ..................................................................................................................... 41
4.12 Host Interface................................................................................................................ 42
4.12.1 2-wire mode .............................................................................................................. 42
4.12.2 3-wire mode .............................................................................................................. 45
5. System Layout Guideline ...................................................................................................... 47
5.1 Power / Ground............................................................................................................. 47
5.2 Signals........................................................................................................................... 47
6. MECHANICAL SPECIFICATION...................................................................................... 49
August 2002
iv C6015-DAT-01B


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List of Figures
gm6015 Preliminary Data Sheet
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
gm6015 System Design Example ............................................................................... 1
gm6015 Pinout Diagram............................................................................................. 4
gm6015 Functional Block Diagram.......................................................................... 11
Using crystal ............................................................................................................. 13
Using oscillator ......................................................................................................... 13
Clock Generation and Distribution ........................................................................... 14
Clock Domains ......................................................................................................... 15
ITU-BT-656.............................................................................................................. 20
8-bit 4:2:2 YCbCr ..................................................................................................... 20
16-bit 4:2:2 YCbCr ................................................................................................... 21
24-bit 4:4:4 YCbCr data ........................................................................................... 21
24-bit RGB data ........................................................................................................ 21
Embedded Sync Extraction....................................................................................... 22
Input Capture Window (HREF/DE enabled)............................................................ 23
Input Capture Window (HREF/DE disabled)........................................................... 24
Relationship between DHS_CS and DSYNCT ........................................................ 27
Gamma correction..................................................................................................... 29
8-bit to 10-bit mapping ............................................................................................. 29
Pre-scale of data for sync insertion (with 8-bit to 10-bit mapping).......................... 30
10-bit to 6-bit dithering............................................................................................. 30
Output Display Windows.......................................................................................... 31
Examples of Different PIP Configurations............................................................... 33
4:3 to 16:9 aspect ratio conversion ........................................................................... 36
16:9 to 4:3 aspect ratio conversion ........................................................................... 37
Inverse 3:2 pulldown processing .............................................................................. 38
2-wire protocol.......................................................................................................... 43
10-bit Register Address ............................................................................................ 45
3-wire protocol.......................................................................................................... 46
Typical SOY_G +/- connection ................................................................................ 47
gm6015 208 pin PQFP dimension ............................................................................ 49
August 2002
v C6015-DAT-01B


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List of Tables
gm6015 Preliminary Data Sheet
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Input Port A ................................................................................................................ 5
Input Port B................................................................................................................. 6
Digital Display Port .................................................................................................... 7
Display Control........................................................................................................... 7
SDRAM Interface Signals .......................................................................................... 8
Host Interface.............................................................................................................. 9
PLL / DDS .................................................................................................................. 9
General Purpose I/O ................................................................................................... 9
Power and Ground ...................................................................................................... 9
Bootstrap Configuration ........................................................................................... 12
Input Video Data Bus Mapping On Port A and Port B ............................................ 16
Input Port B bit[23..18] used as output pins ............................................................. 19
Input Port pins for OSD interface ............................................................................. 20
Digital Output Port Pin Configuration...................................................................... 26
Host Protocol Configuration..................................................................................... 42
Instruction byte format.............................................................................................. 44
August 2002
vi C6015-DAT-01B


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gm6015 Preliminary Data Sheet
1. OVERVIEW
The Genesis Microchip gm6015 display processor is a low-cost, high-quality video processor for
progressive TV (480p), digital TV (DTV) and high definition TV (HDTV) applications. The highly
integrated gm6015 includes dual digital video inputs for MAIN and PIP display, dual bi-level / tri-level
sync separators, “pixel-based” motion adaptive de-interlacing, 2:2/3:2 inverse pull-down film
processing, diagonal processing, arbitrary shrink/zoom scaling on both MAIN and PIP channels, , “3D”
noise reduction filter, SDRAM controller, color space conversion, color controls, video look up table
(VLUT) and multi-image PIP display.
1.1 Applications
SDTV, HDTV and DTV
Flat panel TV (LCD, PDP)
Set-top box
Scan converter box
1.2 System Design Example
Figure 1 below shows a XGA LCD TV system block diagram using gm6015. Designs based on gm6015
will benefit from its high integration and flexibility, which result in lower system cost and design for
multi-platform approach.
S-Video
CVBS 1
CVBS 2
OSD
Video
Decoder
Video
Decoder
4:2:2/4:4:4
YCbCr/RGB
16/24
4:2:2/4:4:4
YCbCr/RGB
16/24
gm6015
MAIN
Output
PIP
Digital
RGB,
HS, VS
XGA
LCD Panel
SDRAM
RF
Tuner
Power
Supply
MCU
Audio
August 2002
Figure 1. gm6015 System Design Example
1
C6015-DAT-01B


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gm6015 Preliminary Data Sheet
1.3 gm6015 Features
Dual Digital Input Port
- Interface compatible with common NTSC/PAL/SECAM video decoders, YPbPr/YUV/RGB
digitizers, MPEG decoders and DVI receivers.
- Bi-level and tri-level sync strip / processing.
- Support for 8/16/24-bit 4:2:2/4:4:4 CCIR 656/601 YCbCr and RGB inputs.
- Programmable input capture size allows input of various SDTV / HDTV resolutions.
- Flexible input port configuration for various video format and data bus width.
- Clamp pulse generation for ADC interface.
- Progressive / Interlace input supported.
- Dual input format measurement units for input timing detection support
- Built-in Wide Screen Signal (WSS) decoder
Digital Output Port
- Embedded (SOG) or separate syncs output.
- Programmable Y C delay (+ / - 3 pixels)
- 4:2:2 / 4:4:4 YCbCr / RGB output formats
- ITU-R BT.656 output supported
- 6 / 8 / 10 bits per channel.
- Programmable MAIN and PIP display size for various VESA / SDTV / HDTV resolutions.
- Bi-level / tri-level sync support
- Progressive / Interlace output
Genesis Proprietary De-interlacing
- Auto detection of film or video source
- 2nd generation adaptive film mode (AFM) de-interlacing.
- Motion adaptive de-interlacing or inverse 3:2/2:2 pull-down de-interlacing on Main channel
- Diagonal processing in MAIN channel
- De-interlacing on PIP channel
Advanced Arbitrary Scaling
- Programmable zoom/shrink scale on MAIN channel allows aspect ratio to be converted or
preserved.
- Programmable zoom/shrink scale on PIP channel allows variable PIP size.
- Panoramic zoom / shrink are supported in MAIN channel
August 2002
2 C6015-DAT-01B


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gm6015 Preliminary Data Sheet
Flexible MAIN / PIP Configuration
- Multiple PIPs supported. A maximum of 16 PIP windows can be displayed.
- Programmable MAIN and PIP positions
- Programmable MAIN background colors
- Programmable PIP border colors.
- Programmable blending levels of PIP display.
- Hi-light border eases active PIP selection in multi-PIP display
- Instantaneous MAIN / PIP swapping
Others
- Integrated triple 256x10-bit video look up table.
- Integrated SDRAM controller. Typically only 1 2M x 32-bit SDRAM is needed.
- Integrated DDS and PLL for clock generation. Only a single low cost 14.31818 MHz crystal is
needed externally.
- Arbitrary up/down frame rate conversion. (e.g. 50Hz to 60Hz, 50Hz to 100Hz, 60Hz to 50Hz,
….etc)
- Input and output color space conversion (CSC)
- Fully programmable color space coefficients and offsets in MAIN and PIP input CSC.
- Bypass channel available
- “3D” noise reduction filter in MAIN channel for standard definition video
- Sharpening filter in MAIN channel with selectable coefficients.
- Programmable interrupt
- Chip activity monitoring circuit.
- OSD interface
- 2-wire or 3-wire SPI host interface
August 2002
3 C6015-DAT-01B


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gm6015 Preliminary Data Sheet
2. PINOUT DIAGRAM
AHS_CS (A656HS)
ARAWHS_CS (ASHS)
ACREF (ACLK2)
AHREF_DE
VSS
VDD
ADATA23 (AOVCOL[2])
ADATA22 (AOVCOL[1])
ADATA21 (AOVCOL[0])
VSS
CVDD
ADATA20 (AOVHS)
ADATA19 (AOVVS)
ADATA18 (AOVACTIV)
ADATA17
ADATA16
ADATA15
ADATA14
ADATA13
ADATA12
ADATA11
ADATA10
ADATA9
ADATA8
ADATA7
ADATA6
ADATA5
VSS
CVDD
ADATA4
ADATA3
ADATA2
ADATA1
ADATA0
VSS_DDS
VDD_DDS
AVSS_DDS
AVDD_DDS
VSS_MPLL
VDD_MPLL
AVSS_MPLL
AVDD_MPLL
AVSS_RPLL
AVDD_RPLL
XTAL
TCLK
AVSS_CSS
BSOY_G+
BSOY_G-
ASOY_G-
ASOY_G+
AVDD_CSS
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
gm6015
104 RAMDQ16
103 RAMDQ17
102 RAMDQ18
101 RAMDQ19
100 RAMDQ20
99 RAMDQ21
98 RAMDQ22
97 RAMDQ23
96 RAMDQ31
95 VSS
94 RAMDQ30
93 RAMDQ29
92 RAMDQ28
91 RAMDQ27
90 RAMDQ26
89 VDD
88 RAMDQ25
87 RAMDQ24
86 CVDD
85 VSS
84 DDATA0
83 DDATA1
82 VSS
81 DDATA2
80 DDATA3
79 DDATA4
78 DDATA5
77 DDATA6
76 DDATA7
75 DDATA8
74 DDATA9
73 DDATA10
72 DDATA11
71 VSS
70 VDD
69 DDATA12
68 DDATA13
67 DDATA14
66 DDATA15
65 DDATA16
64 DDATA17
63 DDATA18
62 DDATA19
61 DDATA20
60 DDATA21
59 VSS
58 DDATA22
57 DDATA23
56 VSS
55 VDD
54 DCLK
53 DODD (GPIO0)
August 2002
Figure 2. gm6015 Pinout Diagram
4
C6015-DAT-01B


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gm6015 Preliminary Data Sheet
I/O Legend: I = Input
Name
ACLK1
AODD
(ACLAMP)
AVS
(A656VS)
(ASVS)
AHS_CS
(A656HS)
ASOY_G+
ASOY_G-
ARAWHS_CS
(ASHS)
ACREF
(ACLK2)
AHREF_DE
ADATA23 (AOVCOL[2])
ADATA22 (AOVCOL[1])
ADATA21 (AOVCOL[0])
ADATA20 (AOVHS)
ADATA19 (AOVVS)
ADATA18 (AOVCLK)
ADATA17 (AOVACTIV)
ADATA16
ADATA15
ADATA14
ADATA13
ADATA12
ADATA11
ADATA10
ADATA9
ADATA8
ADATA7
ADATA6
ADATA5
ADATA4
ADATA3
ADATA2
ADATA1
ADATA0
I/O
I
I
O
I
O
O
I
O
I
I
I
O
I
I
I
I
I
I
I (O)
I (O)
I (O)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
3. PIN DESCRIPTION
O = Output P = Power
G = Ground
Table 1. Input Port A
Pin# Description
154 Port A input clock 1
155 1. Port A odd/even field indicator input (Default)
2. Port A clamp pulse output
156 1. Port A input VS
(Default)
2. Port A VS extracted from 656 data
3. Port A VS extracted from SOG / SOY
157 1. Port A input HS or composite sync (Default)
2. Port A HS extracted from 656 data
207 Port A bi-level / tri-level sync on green / Y
206 Port A bi-level / tri-level sync on green / Y
158 1. Port A raw HS or composite sync (Default)
2. Port A HS extracted from SOG / SOY
159 1. Port A input clock qualifier
(Default)
2. Port A input clock 2
160 Port A input HREF or DE (Data Enable) from DVI receiver
163 1. Port A input data or overlay interface. Please refer to Table 11 for bus selection.
164 2. Overlay interface
165
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
186
187
188
189
190
August 2002
5 C6015-DAT-01B


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Name
BCLK1
BODD
(BCLAMP)
BVS
(B656VS)
(BSVS)
BHS_CS
(B656HS)
BSOY_G+
BSOY_G-
BRAWHS_CS
(BSHS)
BCREF
(BCLK2)
BHREF_DE
BDATA23 (BOVCOL[2], Y_G[1])
BDATA22 (BOVCOL[1], Y_G[0])
BDATA21 (BOVCOL[0], CB_B[1])
BDATA20 (BOVHS, CB_B[0])
BDATA19 (BOVVS, CR_R[1])
BDATA18 (BOVCLK, CR_R[0])
BDATA17 (BOVACTIV)
BDATA16
BDATA15
BDATA14
BDATA13
BDATA12
BDATA11
BDATA10
BDATA9
BDATA8
BDATA7
BDATA6
BDATA5
BDATA4
BDATA3
BDATA2
BDATA1
BDATA0
I/O
I
I
O
I
O
O
I
O
I
I
I
O
I
I
I
I (I, O)
I (I, O)
I (I, O)
I (O, O)
I (O, O)
I (O, O)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
gm6015 Preliminary Data Sheet
Table 2. Input Port B
Pin# Description
7 Port B input clock 1
8 1. Port B odd/even field indicator input (Default)
2. Port B clamp pulse output
9 1. Port B input VS
(Default)
2. Port B VS extracted from 656 data
3. Port B VS extracted from SOG / SOY
10 1. Port B input HS or composite sync (Default)
2. Port B HS extracted from 656 data
204 Port B bi-level / tri-level sync on green / Y
205 Port B bi-level / tri-level sync on green / Y
13 1. Port B raw HS or composite sync (Default)
2. Port B HS extracted from SOG / SOY
14 1. Port B input clock qualifier
(Default)
2. Port B input clock 2
15 Port B HREF or DE (Data Enable) from TMDS receiver
16 1. Port B input data. Please refer to Table 11 for bus selection.
18 2. Overlay interface.
19 3. Output LSB bits of 10-bit per channel output data
20 30-bit YCbCr 4:4:4
22 BDATA[23:22] = Y[1:0]
23 BDATA[21:20] = Cb[1:0]
24 BDATA[19:18] = Cr[1:0]
25 30-bit RGB
28 BDATA[23:22] = G[1:0]
29 BDATA[21:20] = B[1:0]
30 BDATA[19:18] = R[1:0]
31
32
34
35
36
37
38
39
42
43
44
45
46
August 2002
6 C6015-DAT-01B


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Name
DDATA[23]
DDATA[22]
DDATA[21]
DDATA[20]
DDATA[19]
DDATA[18]
DDATA[17]
DDATA[16]
DDATA[15]
DDATA[14]
DDATA[13]
DDATA[12]
DDATA[11]
DDATA[10]
DDATA[9]
DDATA[8]
DDATA[7]
DDATA[6]
DDATA[5]
DDATA[4]
DDATA[3]
DDATA[2]
DDATA[1]
DDATA[0]
Name
DCLK
DVS
(DSYNCT)
DHS_CS
DODD
(GPIO 0)
DDE_BLANK
gm6015 Preliminary Data Sheet
Table 3. Digital Display Port
I/O Pin# Description
O 57
O 58
O 60
O 61
O 62
O 63
O 64
O 65
O 66
O 67
O 68
O 69
O 72
O 73
O 74
O 75
O 76
O 77
O 78
O 79
O 80
O 81
O 83
O 84
Digital display data bus. Please refer to Input Port B for 10-bit RGB / YCbCr 4:4:4 LSB bits
For pin assignment of various video formats please refer to Table 14.
I/O
O
O
O
O
O
I/O
O
Pin#
54
50
49
53
52
Table 4. Display Control
Description
Display output clock
1. Display VSYNC
(Default)
2. Display tri-level sync control
Display HSYNC / composite sync
1. Display field indicator (Default)
2. General purpose I/O pin 0
Note: This is a GPIO pin with DODD as default function. For other GPIO functions, refer to section 4.11.
1. Display data enable / blanking
August 2002
7 C6015-DAT-01B


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Name
RAMCLK
RAMBS0
RAMBS1
RAMCS#
RAMDQ_MSK
RAMWE#
RAM_RAS#
RAM_CAS#
RAMADDR10
RAMADDR9
RAMADDR8
RAMADDR7
RAMADDR6
RAMADDR5
RAMADDR4
RAMADDR3
RAMADDR2
RAMADDR1
RAMADDR0
RAMDQ31
RAMDQ30
RAMDQ29
RAMDQ28
RAMDQ27
RAMDQ26
RAMDQ25
RAMDQ24
RAMDQ23
RAMDQ22
RAMDQ21
RAMDQ20
RAMDQ19
RAMDQ18
RAMDQ17
RAMDQ16
RAMDQ15
RAMDQ14
RAMDQ13
RAMDQ12
RAMDQ11
RAMDQ10
RAMDQ9
RAMDQ8
RAMDQ7
August 2002
gm6015 Preliminary Data Sheet
Table 5. SDRAM Interface Signals
I/O Pin# Description
O 116
O 123
O 122
O 125
O 132
O 131
O 126
O 128
O 121
O 113
O 112
O 111
O 110
O 109
O 108
O 107
O 118
O 119
O 120
I/O 96
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 88
I/O 87
I/O 97
I/O 98
I/O 99
I/O 100
I/O 101
I/O 102
I/O 103
I/O 104
I/O 142
I/O 140
I/O 139
I/O 137
I/O 136
I/O 135
I/O 134
I/O 133
I/O 143
SDRAM clock
SDRAM bank select 0
SDRAM bank select 1
SDRAM chip select
SDRAM data input / output mask
SDRAM write enable
SDRAM row address strobe
SDRAM column address strobe
SDRAM address bus
SDRAM data bus
8
C6015-DAT-01B


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Name
RAMDQ6
RAMDQ5
RAMDQ4
RAMDQ3
RAMDQ2
RAMDQ1
RAMDQ0
Name
/SCS
SCLK
SDATA
/RESET
/IRQ
Name
TCLK
XTAL
Name
GPIO1
GPIO2
Name
AVDD_CSS
AVSS_CSS
AVDD_RPLL
AVDD_MPLL
AVDD_DDS
VDD_PLL
VDD_DDS
AVSS_RPLL
AVSS_MPLL
AVSS_DDS
August 2002
I/O Pin# Description
I/O 144
I/O 145
I/O 148
I/O 149
I/O 151
I/O 152
I/O 153
gm6015 Preliminary Data Sheet
Table 6. Host Interface
I/O Pin# Description
I3
I2
I/O 4
I5
O6
Chip select for 3-wire mode. Active low.
Clock for host interface.
Serial data.
Reset. Active low
Interrupt output. Active low, open drain
Table 7. PLL / DDS
I/O Pin# Description
O 202 Feedback connection to 14.318 MHz crystal. If the reference clock source is a clock oscillator, this
pin should be grounded through a 2.7K pulldown resistor.
I 201 Crystal oscillator input. Connect to 14.318 MHz crystal.
Table 8. General Purpose I/O
I/O Pin# Description
I/O 47
I/O 48
General Purpose I/O
General Purpose I/O
Table 9. Power and Ground
I/O Pin# Description
Composite Sync Separator
P 208 3.3V analog power for composite sync separator
G 203 Analog ground for composite sync separator
PLL / DDS
P 200 3.3V analog power for REFCLK PLL
P 198 3.3V analog power for PROCCLK PLL
P 194 3.3V Analog power for DCLK DDS
P 196 3.3V digital power for DCLK PLL
P 192 3.3V digital power for DDS
G 199 Analog ground for REFCLK PLL
G 197 Analog ground for PROCCLK PLL
G 193 Analog ground for DCLK DDS
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Name
VSS_PLL
VSS_DDS
VDD
CVDD
VSS
I/O
G
G
P
P
G
Pin# Description
195 Digital ground for DCLK PLL
191 Digital ground for DDS
Others
21, 51, 70, 89, 3.3V Power for I/O logic
106, 124, 141,
162,
12, 27, 41, 55, 2.5V Power for core logic
86, 115, 130,
147, 167, 185
1, 11, 17, 26,
Ground
33, 40, 56, 59,
71, 82, 85,
95, 105, 114,
117, 127, 129,
138, 146, 150,
161, 166, 184
gm6015 Preliminary Data Sheet
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4. FUNCTIONAL DESCRIPTION
The block diagram below illustrates the internal functional blocks of gm6015. Each block will be
described in the following sections.
Memory
ASOG_Y+
ASOG_Y-
Analog Sync
Separator
INPUT
PORT A
INPUT
PORT B
MUX
BSOG_Y+
BSOG_Y-
Analog Sync
Separator
CLK
Clock
Generation
IFM
MAIN
Input
Formatter
PIP
Input
Formatter
CSC
CSC
Memory Controller
Main
Main
Image Processor
PIP
PIP
CSC
CSC
IFM
Host
Interface
HOST I/F
OSD
Mixer
Display
Timing
Generator
(DTG)
Output
VLUT
(3x256x10)
H/CS,VS
DE, CLK,
ODD
Sync
Output
Formatter
Digital
Output
Data Bus
Figure 3. gm6015 Functional Block Diagram
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4.1 Reset
gm6015 Preliminary Data Sheet
4.1.1 Hardware Reset
Hardware reset is performed by holding the /RESET pin low for a minimum of 1µs. The clock from
external clock source (typically 14.31818MHz, see Figure 3 and Figure 4) must be present during and
after the reset. All registers will be reset to their default values.
4.1.2 Software Reset
Software reset is performed by setting HOST_CTRL register bit SOFT_RESET to 1. This bit will be
self-cleared to 0 upon completion of reset. The status of each clock domain after reset can be read from
the RESET_STATUS register. All active and status registers will be reset to their default state. Pending
and read/write registers are not affected by software reset.
4.2 Bootstrap Configuration
During hardware reset, some SDRAM interface pins (RAMADDR [10:0], RAMBS[1..0],
RAMDQ_MSK) are configured as inputs. Pull high or pull low resistors (10K) can be placed in these
pins. On the falling edge of /RESET, the value on these lines is captured. This value is readable by the
external microcontroller and is used to configure gm6015 host interface and other user defined options.
Pin Name
Table 10. Bootstrap Configuration
Description
RAMADDR[4:0]
RAMADDR[5]
RAMADDR[6]
RAMADDR[7]
RAMADDR[8]
RAMADDR[9]
RAMADDR[10]
BS0
BS1
DQM
1. If 2-wire protocol is selected, this sets device address bit [5..1].
2. If 3-wire protocol is selected, this pins are ignored.
1. If 2-wire protocol is selected, this sets device address bit [6].
2. If 3-wire protocol is selected :
- pull high to select active drive on SDATA pin
- pull low to select open drain on SDATA pin
1. If 2-wire protocol is selected, this sets device address bit [7].
2. If 3-wire protocol is selected :
- pull high to select transmit on SCLK falling edge and receive on
SCLK rising edge
- pull low to select transmit on SCLK rising edge and receive on
SCLK falling edge
1. Pull high to select 3-wire SPI protocol
2. Pull low to select 2-wire I2C compatible protocol
User defined option 0
User defined option 1
User defined option 2
User defined option 3
User defined option 4
TCLK frequency
1. Pull high
: TCLK frequency > 14.31818 MHz
2. Pull low
: TCLK frequency <= 14.31818 MHz
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4.3 Clock Generation and Distribution
gm6015 has built-in PLLs (Phase Locked Loops) and DDS (Direct Digital Synthesis) to generate all the
clocks necessary for all the functional blocks. Each clock can be programmed to route to various
functional blocks.
4.3.1 External Crystal / Oscillator
Externally a single crystal or TTL/CMOS level clock oscillator is needed. The following two figures
illustrate the use in each case:
+3.3V
Analog Vdd
22pf
22pf
XTAL
14.31818
MHz
47
XTAL
TCLK
2.7k
Analog
Gnd
Figure 4. Using crystal
TCLK
2.7k
Figure 5. Using oscillator
In Figure 4 all components should be placed close to the chip, with a clean analog ground. In Figure 5
the 47resistor should be placed close to the oscillator. The internal oscillating circuit will generate
OSCCLK, which are used by the built-in PLLs to generate all internal clocks, as described in the next
section.
4.3.2 PLL / DDS
The built-in PLLs and DDS are used to generate all internal clocks as well as display clock. The
following is a block diagram of the PLL/DDS block:
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XTAL
TCLK
ACLK1
ACLK2
BCLK1
BCLK2
OSC OSCCLK
Circuit
MUX
REFCLK REFCLK
PLL
PROCCLK
PLL
DIV
DDS
PROCCLK
Domain
REFCLK,
MCUCLK,
IFMCLK
Domains
OPCLK
Domain
IPCLK,
PIPCLK
Domains
Figure 6. Clock Generation and Distribution
The REFCLK PLL is programmed to generate a 171MHz clock which is used by the PROCCLK PLL,
the DDS and other clock domains, namely REFCLK, MCUCLK and IFMCLK domains. REFCLK will
be further divided in MCUCLK and IFMCLK domains.
The PROCCLK PLL is programmed to generate a 100MHz clock to be used by other blocks. The DDS
locks its output frequency (DDSCLK) to the selected input clock (normally the clock for the MAIN
channel) and it can be programmed to generate a wide range of frequency (from 12MHz to 110MHz)
for the display clock.
The following equation is used to calculate the output frequency of the 2 PLLs. MULT and DIV are 5-
bit numbers, with a valid range from 0 to 31 decimal. PDIV is a 2-bit number, with a value of 0 to 3
decimal.
f PLLCLK
=
f OSCCLK
×
MULT + 1
DIV + 1
×
2
1
PDIV
For details in PLL / DDS programming, please refer to “gm6010/6015 Register Programming Guide”
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4.3.3 Clock Domains
ASOG_Y+
ASOG_Y-
IFMCLK Domain
Analog Sync
Separator
IFM
INPUT
PORT A
IPCLK Domain
MAIN
Input
Formatter
CSC
INPUT
PORT B
BSOG_Y+
BSOG_Y-
MUX
PIP
Input
Formatter
CSC
PIPCLK Domain
Analog Sync
Separator
IFM
IFMCLK Domain
CLK
PLLs &
DDS
REFCLK Domain
gm6015 Preliminary Data Sheet
Memory
Memory Controller
Main
Main
Image Processor
PIP
PIP
CSC
CSC
PROCCLK Domain
MCUCLK Domain
Host
Interface
OSD
Mixer
Display
Timing
Generator
(DTG)
Output
VLUT
(3x256x10)
Sync
Output
Formatter
OPCLK Domain
H/CS,VS
DE, CLK,
ODD
Digital
Output
Data Bus
HOST I/F
Figure 7. Clock Domains
Each functional block in gm6015 is driven by a clock which is programmable to come from different
sources. The following is a list of the clock domains in gm6015:
1. IPCLK domain. This is the clock for the MAIN input channel. This will normally come from
ACLK1/ACLK2 or BCLK1/BCLK2, depends on which port is selected as the MAIN channel.
2. PIPCLK domain. This is the clock for the PIP input channel. This will normally come from
ACLK1/ACLK2 or BCLK1/BCLK2, depends on which port is selected as the PIP channel.
3. IFMCLK domain. This is the clock for the IFM and the Analog Sync Separator blocks. This will
normally be driven by the REFCLK PLL divided by 4 (50 MHz clock).
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4. REFCLK domain. This is the clock for the DDS. This comes from the output of the REFCLK PLL
(200 MHz clock).
5. MCUCLK domain. This is the clock for the embedded microcontroller and the gm6015 host
interface. Since this clock drives the host interface, it must have a stable source at reset. At reset,
this clock will be driven by TCLK pin. After the PLLs have had time to lock and settle, the source
of this clock will be automatically switched to REFCLK divided by 4 (50 MHz clock). This
automatic switching can be disabled or overriden by the use of bootstrap inputs (RAMDQ_MSK).
6. PROCCLK domain. This is the video processing and memory interface clock. The filters in MAIN
channel and SDRAM interface run in this clock domain. This comes from the output of the
PROCCLK PLL (100 MHz clock).
7. OPCLK domain. This is the display clock for the chip. This normally comes from the DDS
(programmable frequency locked to IPCLK).
4.4 Input Interface
Two identical digital input ports (Port A and Port B) are provided as interfaces to input video. Each port
can be programmed to accept various input video formats and provide glueless interface to most
NTSC/PAL/SECAM video decoders, YCbCr/RGB digitizers (ADC/PLL), MPEG decoders and
LVDS/TMDS receivers.
4.4.1 Input Port Selection
Both Port A and Port B can be used as the source for MAIN or PIP display. All parameters in MAIN
and PIP input registers (e.g. input capture window size, input lock event, …etc.) need to be set
according to the input video format in each port.
gm6015 allows a very flexible configuration on the data bus going into the input ports. Each 24-bit
input port can be configured to be:
Three 8-bit bus port
One 8-bit bus port and one 16-bit bus port
One 24-bit bus port
RGB or YCbCr data can be connected to any bus in each configuration. However, all the input timing
signal pins (except pixel clock) will also be associated with the data bus selected.
2 input pixel clock pins are available for each input port. The pixel clock to be used can be selected to
come from either Port A or Port B.
The data bus configuration of each input port can be selected by bit[2:0] of MAIN_IP_SRC and
PIP_IP_SRC registers, as shown in the following table :
bit[2:0] =
24 bit RGB
Table 11. Input Video Data Bus Mapping On Port A and Port B
000 001 010
011 100
DATA[23:16]=G
DATA[23:16]=G
DATA[23:16]=R
DATA[23:16]=B
DATA[23:16]=R
101
DATA[23:16]=B
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24 bit YUV 4:4:4
16 bit YUV 4:2:2
8 bit YUV 4:2:2
DATA[15:8]=B
DATA[7:0]=R
DATA[23:16]=Y
DATA[15:8]=U
DATA[7:0]=V
DATA[23:16]=Y
DATA[15:8]=’X’
DATA[7:0]=UV
DATA[23:16]=’X’
DATA[15:8]=’X’
DATA[7:0]=YUV
DATA[15:8]=R
DATA[7:0]=B
DATA[23:16]=Y
DATA[15:8]=V
DATA[7:0]=U
DATA[23:16]=Y
DATA[15:8]= UV
DATA[7:0]=’X’
DATA[23:16]=’X’
DATA[15:8]= YUV
DATA[7:0]=’X’
DATA[15:8]=G
DATA[7:0]=B
DATA[23:16]=V
DATA[15:8]=Y
DATA[7:0]=U
DATA[23:16]= UV
DATA[15:8]=Y
DATA[7:0]=’X’
DATA[23:16]= YUV
DATA[15:8]=’X’
DATA[7:0]=’X’
DATA[15:8]=G
DATA[7:0]=R
DATA[23:16]=U
DATA[15:8]=Y
DATA[7:0]=V
DATA[23:16]= ‘X’
DATA[15:8]=Y
DATA[7:0]=UV
DATA[23:16]= ‘X’
DATA[15:8]=’X’
DATA[7:0]=YUV
DATA[15:8]=B
DATA[7:0]=G
DATA[23:16]=V
DATA[15:8]=U
DATA[7:0]=Y
DATA[23:16]=UV
DATA[15:8]= ‘X’
DATA[7:0]=Y
DATA[23:16]=YUV
DATA[15:8]= ‘X’
DATA[7:0]=’X’
DATA[15:8]=R
DATA[7:0]=G
DATA[23:16]=U
DATA[15:8]=V
DATA[7:0]=Y
DATA[23:16]= ‘X’
DATA[15:8]=UV
DATA[7:0]=Y
DATA[23:16]= ‘X’
DATA[15:8]=YUV
DATA[7:0]=’X’
NOTE :
i) bit[2:0] = ‘110’ or ‘111’ are invalid;
ii) ‘X’ means not used
iii) If output is set to 30-bit RGB or 30-bit 4:4:4 YCbCr, then BDATA[23:18] in input port B are used
as 2 LSB bits of 10-bit output data. In such case the input format in port B will be limited. See
section 4.4.2.9 for detail.
4.4.2 Input Signals
The following sections describe in details all signals associated with the 2 input ports.
NOTE :
Each section describes the pins for both Port A and Port B and both pin names will be shown ;
Some pins have multiple functions and their corresponding pin names are listed for reference. Pin
names in bracket are alternate pin functions which need to be enabled by registers.
4.4.2.1 ACLK1
BCLK1
These are the input pixel clocks and they are qualified by ACREF / BCREF respectively. The sampling
edge of ACLK / BCLK is programmable and the default is rising edge.
4.4.2.2 ACREF (ACLK2)
BCREF (BCLK2)
ACREF / BCREF (Default)
These are the clock qualifiers for ACLK1 / BCLK1 respectively. All data during the sampling edge
of ACLK1 / BCLK1 are ignored when ACREF / BCREF is inactive.
ACLK2 / BCLK2
These serve as a second input pixel clock pins. When a input port is divided into 2 input data bus,
these pins can be used as the input pixel clock for each of the data bus.
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4.4.2.3 AODD (ACLAMP)
BODD (BCLAMP)
AODD / BODD (Default)
These are the odd / even field indicator input pins and are usually driven by video decoder or MPEG
decoder.
ACLAMP / BCLAMP
These are the clamp pulse output pins and are usually connected to external ADC to restore the dc
level of analog input signal. Location of the start and end of clamp pulse is programmable.
4.4.2.4 AVS (A656VS, ASVS)
BVS (B656VS, BSVS)
AVS / BVS (Default)
These pins serve as input vsync pins and are usually connected to video decoder or MPEG decoder.
A656VS / B656VS
These pins serve as output vsync pins that are extracted from input video in ITU-BT-656 format.
They can be used by external devices which need vsync signal for other timing purposes.
ASVS / BSVS
These pins serve as output vsync pins that are extracted from input video with embedded sync on
green or Y channel (SOG or SOY). They can be used by external devices which need vsync signal
for other timing purposes.
4.4.2.5 AHS_CS (A656HS)
BHS_CS (B656HS)
AHS_CS / BHS_CS (Default)
These pins serve as input hsync or composite sync pins and are usually connected from input video
decoder or MPEG decoder. For composite sync input, the vsync and hsync will be extracted by the
built-in sync separator and can be routed internally to the MAIN and PIP channels. See section
4.4.4.2 “Analog Sync Separator” for detail.
A656HS / B656HS
These pins serve as output hsync pins that are extracted from input video in ITU-BT-656 format.
They can be used by external devices which need hsync signal for other timing purposes.
4.4.2.6 ASOY_G+, ASOY_G-
BSOY_G+, BSOY_G-
These are differential input sync pins for analog input video with sync signals embedded on green or Y
channel. The embedded sync signals will be extracted by the built-in sync separator and can be routed
internally to the ASHS / BSHS (for hsync) pins and ASVS / BSVS (for vsync) pins.
4.4.2.7 ARAWHS_CS (ASHS)
BRAWHS_CS (BSHS)
ARAWHS_CS / BRAWHS_CS (Default)
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These pins serve as the raw (unprocessed) input hsync / composite sync pins and they are used for
input format measurement
ASHS / BSHS
These pins serve as output hsync pins that are extracted from input video with embedded sync on
green or Y channel (SOG or SOY).
4.4.2.8 AHREF_DE
BHREF_DE
These are input signals which indicate the presence of active video pixels in a line. HREF signals are
usually present in video decoders and DE (Data Enable) signals are usually present in TMDS receivers.
All pixels located at the inactive region of these signals are ignored and not processed.
4.4.2.9 ADATA [23:0]
BDATA [23:0]
These are the input video data bus for each port. Video data can be connected to different buses of the
same input port. See “Input Port Selection” section for configuration.
ADATA [23:17] and BDATA[23:17] can also be used to interface with external character based OSD
(On Screen Display) devices. See next section for details in OSD interface.
NOTE:
When the digital output port is set to output 10-bit per channel RGB or YCbCr 4:4:4 format,
BDATA[23:18] will be used as the 2 LSB bits (bit 1 and bit 0) of 10-bit data, as follows:
Table 12. Input Port B bit[23..18] used as output pins
30-bit RGB
30-bit 4:4:4
YCbCr
BDATA[23]
G[1]
Y[1]
BDATA[22]
G[0]
Y[0]
BDATA[21]
B[1]
Cb[1]
BDATA[20]
B[0]
Cb[0]
BDATA[19]
R[1]
Cr[1]
BDATA[18]
R[0]
Cr[0]
As a result, the input video format that can be applied to input port B is limited to a maximum of 16 bits
wide data.
4.4.2.10 AOVACTIV, AOVCLK, AOVVS, AOVHS, AOVCOL [2:0]
BOVACTIV, BOVCLK, BOVVS, BOVHS, BOVCOL [2:0]
These are the pins used for interface to external character based OSD devices (such as Motorola
MC141544, etc.). These pins are multiplexed with ADATA[23:17] / BDATA [23:17] and when they are
used as OSD interface, the number of video format supported in the corresponding input port will be
limited..
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Input Port A
ADATA[17]
ADATA[18]
ADATA[19]
ADATA[20]
ADATA[21]
ADATA[22]
ADATA[23]
Table 13. Input Port pins for OSD interface
Input Port B OSD in Port A OSD in Port B OSD Function
BDATA[17] AOVACTIV
BOVACTIV
OSD active indicator
BDATA[18] AOVCLK
BOVCLK
OSD pixel clock
BDATA[19] AOVVS
BOVVS
OSD vsync
BDATA[20] AOVHS
BOVHS
OSD hsync
BDATA[21] AOVCOL[0]
BOVCOL[0]
OSD color data [0]
BDATA[22] AOVCOL[1]
BOVCOL[1]
OSD color data [1]
BDATA[23] AOVCOL[2]
BOVCOL[2]
OSD color data [2]
Note that although both Port A and Port B have overlay interface, only one can be used at a time.
4.4.3 Input Video Formats
The following video formats are supported by gm6015 input ports :
ITU-BT-656
8-bit 4:2:2 YCbCr
16-bit 4:2:2 YCbCr
24-bit 4:4:4 YCbCr
24-bit RGB
The timing of these video formats are shown in the following figures :
VCLK
YCbCr
Blanking FF 00 00 SAV Cb Y Cr Y Cb Y
1710 1711 1712 1713 1714 1715 0 1 2 3 4 5
Y Cr Y FF 00 00 EAV Blanking
1437 1438 1439 1440 1441 1442 1443 1444
Preamble
Timing Reference word
SAV (Start of Active Video)
Active Video
Preamble
Timing Reference word
EAV (End of Active Video)
Figure 8. ITU-BT-656
ACLK
YCbCr
August 2002
Cb0 Y0 Cr0 Y1
~
Cr718
Y719
Figure 9. 8-bit 4:2:2 YCbCr
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ACLK
Y
CbCr
Y0 Y1 Y2
Cb0 Cr0 Cb2
~
Y717
Y718
Y719
~
Cr716
Cb718
Cr718
Figure 10. 16-bit 4:2:2 YCbCr
ACLK
Y
Cb
Cr
Y0 Y1 Y2
~
Y717
Y718
Y719
Cb0 Cb1 Cb2
~
Cb717
Cb718
Cb719
Cr0 Cr1 Cr2
~
Cr717
Cr718
Cr719
Figure 11. 24-bit 4:4:4 YCbCr data
ACLK
R
G
B
R0 R1 R2
~
R717
R718
R719
G0 G1 G2
~
G717
G718
G719
B0 B1 B2
~
B717
B718
B719
Figure 12. 24-bit RGB data
4.4.4 Input Sync Processing
For input video without separate sync signals, gm6015 has built-in 656 decoder and sync separator to
extract embedded sync information. These extracted sync signals can be routed to external pins to be
used by external logic for other timing purposes. The figure below illustrates how embedded syncs are
extracted and routed to external pins.
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SOY_G+
SOY_G-
RAW HS_CS
656 Data
VS
HS_CS
Analog Sync
Separator
gm6015 Preliminary Data Sheet
D igital Sync
S e p a ra to r
SVS
SHS
656 Decoder
656VS
656HS
VSYNC
HSYNC
Input
P ro c e s s in g
Figure 13. Embedded Sync Extraction
4.4.4.1 656 Decoder
ITU-BT-656 video format consists of pixel clock and 8 bits of data. No separate hsync, vsync and odd
signals are present. Timing data is embedded in the data stream. The internal 656 decoder will extract
the hsync, vsync and odd signals from the embedded timing data. The extracted hsync and vsync can be
routed internally to A656HS / B656HS and A656VS / B656VS pins.
4.4.4.2 Analog Sync Separator
For video format with sync signals embedded on the analog video data, gm6015 built-in analog sync
separator can extract the embedded sync signals. Bi-level and tri-level sync are supported. The analog
sync separator acts as a “sync slicer” to the analog signal and generates digital composite sync signal to
be processed by the digital sync separator.
For details in the operation of analog sync separator, please see “gm6010/6015 Hardware Theory of
Operation”
4.4.4.3 Digital Sync Separator
The digital sync separator takes the digital composite sync signal generated from analog sync separator
and output separate hsync and vsync signals. The generated hsync signal is of constant period which
means all equalization pulses are eliminated.
In addition, the digital sync separator also provides measurement and status on sync signals to the host
interface.
For details in the operation of digital sync separator, please see “gm6010/6015 Hardware Theory of
Operation”
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4.4.5 Input Capture Window
Figure 14 and Figure 15 illustrate the input capture window with active and cropped video. Note that
the horizontal and vertical start location is controlled by how bit 2 of IP_MISC_CTRL register is set:
IP_MISC_CTRL bit 2 = 0 (HREF_DE signal disabled)
The horizontal start location is the number of clocks (qualified by CREF) from the leading edge of
HSYNC to the 1st active pixel.
The vertical start location is the number of lines from the leading edge of VSYNC to the 1st active
line.
IP_MISC_CTRL bit 2 = 1 (HREF_DE signal enabled)
The horizontal start location is the number of clocks (qualified by CREF) from the leading edge of
HREF to the 1st active pixel.
The vertical start location is the number of lines from the leading edge of the 1st HREF after
VSYNC to the 1st active line.
HREF
HSYNC
Horizontal Active
Start
Vertical Active Start
Horizontal Active Width
BLANKING
ACTIVE VIDEO
Vertical Active Length
CROPPED ACTIVE VIDEO
Figure 14. Input Capture Window (HREF/DE enabled)
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HREF
HSYNC
Horizontal Active
Start
Vertical Active Start
Vertical Active Length
gm6015 Preliminary Data Sheet
Horizontal Active Width
BLANKING
ACTIVE VIDEO
CROPPED ACTIVE VIDEO
Figure 15. Input Capture Window (HREF/DE disabled)
Input cropping is supported by means of programming the start location and active width/length. The
video data that gm6015 will process is the portion named “Cropped Active Video” in Figure 14 and
Figure 15.
4.4.6 Input Format Measurement
The gm6015 has an Input Format Measurement block (IFM) providing the capability of measuring the
horizontal and vertical timing parameters of the input video source. This information may be used to
determine the video format and to detect a change in the input format.
Horizontal measurements are measured in terms of the selected IFM_CLK, while vertical measurements
are measured in terms of HSYNC pulses.
4.4.6.1 Measurement
The IFM is able to measure the horizontal period and active high pulse width of the HSYNC signal, in
terms of the selected clock. Horizontal measurements are performed on only a single line per frame (or
field). The line used is programmable. It is able to measure the vertical period and VSYNC pulse width
in terms of rising edges of HSYNC. When using composite sync input, these measurements use the
internally synthesized HSYNC and VSYNC signals.
Once enabled, measurement begins on the rising VSYNC and is completed on the following rising
VSYNC. The measurement will stop after it is completed unless enabled again.
August 2002
24 C6015-DAT-01B





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