Fairchild Semiconductor Electronic Components Datasheet


FDS6930B

Dual N-Channel Logic Level PowerTrench MOSFET



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June 2005
FDS6930B
Dual N-Channel Logic Level PowerTrench® MOSFET
Features
5.5 A, 30 V. RDS(ON) = 38 m@ VGS = 10 V
RDS(ON) = 50 m@ VGS = 4.5 V
Fast switching speed
Low gate charge
High performance trench technology for extremely
low RDS(ON)
High power and current handling capability
General Description
These N-Channel Logic Level MOSFETs are produced using
Fairchild Semiconductor’s advanced PowerTrench process that
has been especially tailored to minimize the on-state resistance
and yet maintain superior switching performance.
These devices are well suited for low voltage and battery pow-
ered applications where low in-line power loss and fast switch-
ing are required.
D2
D2
D1
D1
SO-8
Pin 1
G2
S2
G1
S1
54
63
72
81
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
PD
Drain-Source Voltage
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1)
(Note 1a)
(Note 1b)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1c)
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Ratings
30
± 20
5.5
20
2
1.6
1
0.9
–55 to 150
78
40
Package Marking and Ordering Information
Device Marking
FDS6930B
Device
FDS6930B
Reel Size
13"
Tape width
12mm
Units
V
V
A
W
°C
°C/W
°C/W
Quantity
2500 units
©2005 Fairchild Semiconductor Corporation
FDS6930B Rev. A
1
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Electrical Characteristics TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
BVDSS
TJ
IDSS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
IGSS
Gate–Source Leakage
On Characteristics (Note 2)
VGS = 0 V, ID = 250 µA
ID = 250 µA, Referenced to 25°C
VDS = 24 V, VGS = 0 V
VDS = 24 V, VGS = 0 V, TJ = 55°C
VGS = ±20 V, VDS = 0 V
VGS(th)
VGS(th)
TJ
RDS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
ID(on)
On–State Drain Current
gFS Forward Transconductance
Dynamic Characteristics
VDS = VGS, ID = 250 µA
ID = 250 µA, Referenced to 25°C
VGS = 10 V, ID = 5.5 A
VGS = 4.5 V, ID = 4.8 A
VGS = 10 V, ID = 5.5 A, TJ = 125°C
VGS = 10 V, VDS = 5 V
VDS = 5 V, ID = 5.5 A
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
RG Gate Resistance
Switching Characteristics (Note 2)
VDS = 15 V, V GS = 0 V,
f = 1.0 MHz
VGS = 15 mV, f = 1.0 MHz
td(on)
tr
Turn–On Delay Time
Turn–On Rise Time
VDD = 15 V, ID = 1 A,
VGS = 10 V, RGEN = 6
td(off)
Turn–Off Delay Time
tf Turn–Off Fall Time
Qg Total Gate Charge
Qgs Gate–Source Charge
VDS = 5 V, ID = 5.5 A,
VGS = 5 V
Qgd Gate–Drain Charge
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current
VSD
Drain–Source Diode Forward Voltage
VGS = 0 V, IS = 1.3 A (Note 2)
trr
Diode Reverse Recovery Time (note3)
IF = 5.5 A, diF/dt = 100 A/µs
Qrr Diode Reverse Recovery Charge
Min Typ Max Units
30
26
V
mV/°C
1
10
±100
µA
nA
1 1.9 3
V
–4.6 mV/°C
31 38 m
40 50
45 62
20 A
19 S
310 412
90 120
40 60
1.9
pF
pF
pF
6 12
6 12
16 28
24
2.7 3.8
1.0
0.7
ns
ns
ns
ns
nC
nC
nC
1.3
0.8 1.2
16 32
6
A
V
nS
nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 78°C/W when mounted
on a 0.5 in2 pad of 2 oz
copper
b) 125°C/W when
mounted on a 0.02 in2
pad of 2 oz copper
c) 135°C/W when
mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. Trr parameter will not be subjected to 100% production testing.
FDS6930B Rev. A
2
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Typical Characteristics
20
VGS = 10V
4.0V
16
6.0V
12
4.5V
3.5V
8
3.0V
4
0
0 0.5 1 1.5 2
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
1.6
ID = 5.5A
VGS = 10.0V
1.4
1.2
1
0.8
0.6
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. On-Resistance Variation with
Temperature.
20
VDS = 5V
16
12
8
TA = 125° C
-55°C
4
25°C
0
1234
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
5
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2
1.8
VGS = 3.5V
1.6
1.4 4.0V
1.2
1
4.5V
5.0V
6.0V
10.0V
0.8
0
4 8 12 16
ID, DRAIN CURRENT (A)
20
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.12
0.1
ID = 2.75A
0.08
0.06
TA = 125°C
0.04
TA = 25°C
0.02
2
468
VGS, GATE TO SOURCE VOLTAGE (V)
10
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
VGS = 0V
10
1
0.1
0.01
TA = 125°C
25°C
-55°C
0.001
0.0001
0
0.2 0.4 0.6 0.8
1
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS6930B Rev. A
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Typical Characteristics
10
ID = 5.5A
8
6
4
VDS = 5V
15V
10V
2
0
0123456
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
10 RDS(ON) LIMIT
100µs
1ms
10ms
100ms
1s
1 10s
DC
VGS = 10.0V
0.1 SINGLE PULSE
RθJA = 135°C/W
TA = 25°C
0.01
0.01
0.1 1 10
VDS, DRAIN-SOURCE VOLTAGE (V)
100
Figure 9. Maximum Safe Operating Area.
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500
f = 1 MHz
VGS = 0 V
400
300
200
100
Crss
0
0
Coss
Ciss
5 10 15
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
Figure 8. Capacitance Characteristics.
50
SINGLE PULSE
40
RθJA = 135°C/W
TA = 25°C
30
20
10
0
0.001
0.01
0.1 1
t1, TIME (sec)
10
Figure 10. Single Pulse Maximum
Power Dissipation.
100
1
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA(t) = r(t) * RθJA
RθJA = 135°C/W
P(pk)
t1
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
0.001
0.0001
0.001
0.01
0.1 1
t1, TIME (sec)
10 100 1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS6930B Rev. A
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TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
FAST®
ActiveArray™ FASTr™
Bottomless™ FPS™
Build it Now™ FRFET™
CoolFET™
GlobalOptoisolator™
CROSSVOLTGTO™
DOME™
HiSeC™
EcoSPARK™ I2C™
E2CMOS™
i-Lo
EnSigna™
ImpliedDisconnect™
FACT™
IntelliMAX™
FACT Quiet Series™
Across the board. Around the world.™
The Power Franchise®
Programmable Active Droop™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerEdge™
PowerSaver™
PowerTrench®
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
μSerDes™
SILENT SWITCHER®
SMART START™
SPM™
Stealth™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic®
TINYOPTO™
TruTranslation™
UHC™
UltraFET®
UniFET™
VCX™
Wire™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TOANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUMEANY LIABILITY
ARISING OUT OF THEAPPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEYANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTENAPPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
effectiveness.
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I16





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